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Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are of little value if they cannot be verified through Formal Equivalence Verification (FEV). FEV setup must be… Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
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Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. Packaging technologies for 2.5D and 3DIC are becoming more… Protocol and Memory Interface Verification in the Shrinking World of 3DIC
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Xcelium Apps: Everything You Need in the Simulation Metaverse
Register for this CadenceTECHTALK if you are looking for an end-to-end solution for all your verification requirements in automotive, mobile, and hyperscale designs. This CadenceTECHTALK introduces Xcelium Apps, a portfolio of domain-specific technologies implemented natively on the Cadence Xcelium Logic Simulator. The Xcelium Apps are a paradigm shift in the way verification is being done,… Xcelium Apps: Everything You Need in the Simulation Metaverse
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Victory Visual, Silvaco’s New Graphical Visualization Solution for TCAD
Victory Visual is a new graphical post processing tool for use with all Silvaco TCAD simulators. It is an integral part of the TCAD Interactive Tools suite. Victory Visual can operate standalone or along with other Silvaco TCAD tools, such as DeckBuild. While users of TonyPlot or TonyPlot3D will find some of the functionality familiar,… Victory Visual, Silvaco’s New Graphical Visualization Solution for TCAD
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From MATLAB to Optimized RTL in Minutes
As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from design implementation, often resulting in late discovery of performance issues. To mitigate this challenge, Cadence and MathWorks have collaborated to… From MATLAB to Optimized RTL in Minutes
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The Keys to SystemC & TLM-2.0: How to be Successful
SystemC has become well-established as the language of choice for system modeling and virtual platform creation and integration, and is now being applied successfully for high level synthesis. SystemC models also frequently appear as reference models in the hardware verification flow. This session is aimed at hands-on hardware or software engineers who might know Verilog… The Keys to SystemC & TLM-2.0: How to be Successful
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International Test Conference
Disneyland Hotel 1150 West Magic Way, Anaheim, CA, United StatesWe are back live and what a grand place to have our first live event in three years; Disneyland! We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products! ITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play… International Test Conference
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Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
The West Anaheim Resort 1030 West Katella Avenue, Anaheim, CA, United StatesAs a member of the design and test community, you are invited to attend Synopsys 28th Annual Test & SLM Special Interest Group (SIG) at the 2022 International Test Conference (ITC). This year’s event will be hosted by Dr. Ken Butler, Senior Director of Business Development from Advantest. Dr. Butler will be joined by experts… Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
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U.S. Executive Forum
The 2022 GSA U.S. Executive Forum is coming up on September 27 in Menlo Park, California. USEF 2022 is one of the most anticipated GSA events of the year and attendance is filling up quickly. Make sure to secure your spot before it's too late. In this unique and exclusive gathering, thought leaders, visionaries and innovators… U.S. Executive Forum
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Global Foundries Technology Summit – EMEA
GlobalFoundries Fab 1 Wilschdorfer Landstrasse 101, Dresden, GermanyDAY 1 Wednesday, September 28, 2022 Doors Open 3:00pm CET DINNER Restaurant KULTURWIRTSCHAFT, 7pm - 10pm DAY 2 Thursday, September 29, 2022 Doors Open 8:30am CET EVENT LOCATION GlobalFoundries FAB 1 Wilschdorfer Landstrasse 101 01109 Dresden, Germany We are thrilled to welcome you to GF Technology Summit 2022. This exclusive, invitation-only event… Global Foundries Technology Summit – EMEA
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Silicon Realization TechSummit
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesThis year's event brings together Synopsys' Digital Design Technical Symposium and Verification Day into a single event - Synopsys Silicon Realization TechSummit. This one-day, in-person event is designed to inform executives, managers, and design and verification engineers about how the EDA industry is evolving. What Attendees Can Expect A keynote and presentations from leaders in… Silicon Realization TechSummit
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Architecture Exploration of Automotive Networks, Radars, and Semiconductors
The buzzwords of 2022 are autonomous driving, radars, and semiconductor and they are all similar in more than one-way. All have protocols, schedulers, sensors, high performance computing, software, networks, interfaces, antennas, and attenuators. VisualSim Architect is used to architect and verify all these applications. Join us for this Webinar on Commonality in the Architecture Exploration… Architecture Exploration of Automotive Networks, Radars, and Semiconductors
12 events found.