-
-
Samsung Foundry Forum & SAFE Forum 2022 – US
Signia by Hilton 170 S Market Street, San Jose, CA, United StatesThrough the various session programs, clients, partners, and experts in each field will be able to meet again in person and prepare to go forth into the new future of… Samsung Foundry Forum & SAFE Forum 2022 – US
-
PCB West 2022
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesFor more than 30 years PCB West has trained designers, engineers, fabricators and, lately, assemblers on making printed circuit boards for every product or use imaginable. More than 2,500 designers,… PCB West 2022
-
Post-layout Circuit Sizing Optimization
My IC design career started out with manually sizing transistors to improve performance, while minimizing layout area and power consumption. Fortunately we don’t have to do manual transistor sizing anymore,… Post-layout Circuit Sizing Optimization
-
2022 IEEE Electronic Design Process Symposium (EDPS)
SEMI 673 S. Milpitas Blvd, Milpitas, CA, United StatesWe are planning to hold 2022 IEEE EDPS live! Looking forward to meeting with you face-to-face. About this event 2022 IEEE EDPS will be held on Oct 6 and Oct… 2022 IEEE Electronic Design Process Symposium (EDPS)
-
IESA Vision Summit 2022
The LaLIT Bangalore, IndiaThe 17th edition of IESA flagship event, IESA Vision Summit 2022 is scheduled on 12th and 13th October 2022 in Bengaluru. This is our flagship event where most of the… IESA Vision Summit 2022
-
Everything You Need to Know About Virtual ECU Abstraction Levels
Growing electronic/electrical (E/E) architecture complexity and software content in modern vehicles has propelled the use of virtualization-based testing to develop and validate functions and software components more effectively. The simulation… Everything You Need to Know About Virtual ECU Abstraction Levels
-
Assertions-Based Verification for VHDL Designs
Assertion-based verification (ABV) enables the use of assertions for the efficient verification of low-level design properties. These assertions could be verified by simulation and formal verification methods. The VHDL 2008… Assertions-Based Verification for VHDL Designs
-
SNUG Europe
Hilton Munich Airport Terminalstraße Mitte 20, 85356 München-Flughafen, Munich, GermanySince 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings… SNUG Europe
-
Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
Demand for next-generation wireless communication, aerospace, and transportation systems is driving the need for high-performance, cost-sensitive silicon RFICs and III-V compound semiconductor monolithic microwave integrated circuits (MMICs), often integrated into advanced system-in-package (SiP) modules.… Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
-
Improving Efficiency and Quality of Verification Environments with Automation
Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent… Improving Efficiency and Quality of Verification Environments with Automation
-
RISC-V Con
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesIn order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the… RISC-V Con
-
Synopsys Photonic Symposium
Photonics and photonic IC technologies are crucial to support rapidly evolving internet, healthcare, mobility, and security needs. Driven by data communications, photonic ICs are moving rapidly from the laboratory to… Synopsys Photonic Symposium
12 events found.