-
RISC-V Days Tokyo 2023 Summer
Ito International Research Center The University of Tokyo, Tokyo, JapanRISC-V Day Tokyo 2023 Summer Conference is Japan’s largest RISC-V real event. RISC-V Day Tokyo 2023 Summer Conference will be held on June 20, 2023 (Tuesday) from 9:00 to 20:30 Japan time (JST). A real presentation will be held at Ito Hall ( B2 floor of Ito International Research Center, the University of Tokyo ).… RISC-V Days Tokyo 2023 Summer
-
Leveraging Silicon Lifecycle Management (SLM) for Automotive Applications
Automobiles are today’s supercomputers and with that statement comes great challenges. A vehicle is a highly demanding environment for electronics. Temperature and humidity extremes, noise and vibration, electrical interference, exposure to alpha particles, and other factors all make it hard to design and manufacture chips that will operate correctly under all conditions. In addition, the… Leveraging Silicon Lifecycle Management (SLM) for Automotive Applications
-
Applying AI/ML Technology for Rapid Design Optimization
The problem of optimization is a long-standing one in the field of design. For years, the most conventional approach was the brute-force method of running parametric sweeps on the design space. However, as systems become more complex and the number of parameters increases, the computational resource and time cost becomes unsustainable. With the Cadence Optimality… Applying AI/ML Technology for Rapid Design Optimization
-
Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
When designers synthesize chip designs with aggressive PPA targets, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of optimization techniques such as retiming, multibit banking and advanced data-path optimizations, though these techniques can end up… Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
-
Design and Analysis of Multi-Die & 3D-IC Systems
The architecture and heterogeneous integration capability of 3D-IC (three-dimensional integrated circuits) offer many benefits. The latest configuration methods, CoWoS (Chip On Wafer on Substrate) and WoW (Wafer on Wafer) from TSMC, provide advantages by significantly reducing the interconnect length and signal power loss. These new technologies have introduced the need for innovative ways to solve… Design and Analysis of Multi-Die & 3D-IC Systems
-
Verification Futures 2023 UK
University of Reading Whiteknights Campus Park House, Reading, United KingdomThe Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides… Verification Futures 2023 UK
-
DVCon Japan 2023
Kawasaki CIty Industrial Promotion Hall Kawasaki City, JapanThe Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees… DVCon Japan 2023
-
How AI and Semiconductors Will Drive Innovation and Productivity
Semiconductors are critical to the functioning of the modern world driving economic competitiveness, national security, and technologies ranging from modern defense capabilities to autonomous vehicles. Artificial Intelligence and the hardware used in this platform are impacting how the world will use information to increase productivity. The semiconductors used in these platforms are instrumental to its… How AI and Semiconductors Will Drive Innovation and Productivity
-
Dealing with Complexity in Formal through Abstraction and Reduction
In the world of formal verification, abstractions along with design reductions, help reduce the state space and make it easier for formal to converge on its proofs. In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore the process of abstraction, safe design reductions, and when to use them. Doug will show practical… Dealing with Complexity in Formal through Abstraction and Reduction
-
European Nanoelectronics Applications Design and Technology Conference
Y-SPOT Building 5, Place Nelson Mandela, Grenoble, FranceFOCUS The European Nanoelectronics Applications, Design & Technology Conference will focus on electronic components, electronic system design, design automation, and manufacturing topics related to micro- and nanoelectronics, which are critical to success for many European companies. Exhaustive research and development in this area have been supported by EUREKA, Horizon Europe, and local governments in recent… European Nanoelectronics Applications Design and Technology Conference
-
2023 Andes RISC-V CON
The DoubleTree by Hilton 2050 Gateway Place, San Jose, CA, United StatesRISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility.… 2023 Andes RISC-V CON
-
Verisium Debug for UPF Low Power Design
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. What you… Verisium Debug for UPF Low Power Design
12 events found.