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From Cross-Platform Specification to Code Generation at the Enterprise Level
Learn how to capture your register and sequence specifications for IPs and SoCs from the individual IP to the enterprise level using IDS-NextGen™ .
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Complete STA Workshop with OpenSTA
In this program you will get access to: 10 hours of training videos access for the lifetime Access to reading material with sample codes for the lifetime 1.5hr Q/A sessions… Complete STA Workshop with OpenSTA
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AI-Driven Verification: Saving Time with Verdi Regression Debug Automation
Analyzing the thousands of failures from daily regression runs is a manual, tedious, and error-prone process. The process can significantly impact quality-of-results, time-to-results and cost-of-results. The Synopsys Verdi® Regression Debug… AI-Driven Verification: Saving Time with Verdi Regression Debug Automation
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EMC+SIPI 2022
The Spokane Convention Center 334 W Spokane Falls Blvd, Spokane, WA, United StatesEMC+SIPI 2022 leads the industry in providing state-of-the-art education on EMC and Signal Integrity and Power Integrity techniques. On behalf of the IEEE EMC Society, I invite you to join… EMC+SIPI 2022
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Flash Memory Summit
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesProgram It is ideal for consumer applications such as cellphones, digital cameras, and music players, and is also useful in computers, communications systems, and military/defense applications. It can replace hard… Flash Memory Summit
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Advanced Physical Design using OpenLANE/Sky130
Physical Design or PnR (Place and Route) is the core of any IC design cycle. From a RTL netlist to final tape-out, each phase of PnR brings it’s own challenges… Advanced Physical Design using OpenLANE/Sky130
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A Smart and Automatic Assembly and Connections for SoCs
Learn how to automatically assemble and connect IPs from many different sources at your SoC level using SoC Enterprise™. This includes automatic generation of components such as aggregators, bridges, channels,… A Smart and Automatic Assembly and Connections for SoCs
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2022 R2: What’s New in Ansys Signal & Power Integrity
About this Event The 2022 R2 Ansys Signal and Power Integrity release introduces significant simulation improvements for electronic printed circuit boards, IC packages, and interposers. Ansys SIwave delivers new features,… 2022 R2: What’s New in Ansys Signal & Power Integrity
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Has the Time for Analog Automation Finally Come?
The semiconductor industry is experiencing explosive growth, driven by emerging applications such as AI, 5G, IoT and automotive. To keep pace, design teams have deployed sophisticated CAD tools that can… Has the Time for Analog Automation Finally Come?
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Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory Process
When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco… Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory Process
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CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
Moderators: Ankur Srivastava (U. of Maryland) and Swarup Bhunia (U. of Florida) Panelists: - Mike Borza, Synopsys - Brian Night, Microsoft - Pompei Len Orlando, Air Force Research Lab (AFRL)… CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
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Fast and Accurate Functional ECOs with Synopsys Formality ECO
To achieve maximal quality of results (QoR) in synthesis, it requires leveraging retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys Fusion Compiler™ implementation solution. However,… Fast and Accurate Functional ECOs with Synopsys Formality ECO
12 events found.