Democratizing IC Design: The IEEE SSCS PICO Program
Inspired by the possibilities of open-source chip design, the IEEE Solid-State Circuits Society (SSCS) launched its new Platform for IC Design Outreach (PICO) in the summer of 2021. With this program, the SSCS intends to contribute to the new open source movement, forge connections with the fast-growing open source community and help educate next-generation IC… Read More »Democratizing IC Design: The IEEE SSCS PICO Program
Chiplet Summit
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesThe First Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions of the experts,… Read More »Chiplet Summit
Signal Integrity Issues for Silicon Interposers
The development of applications like high-performance computing, Artificial Intelligence (AI) processors, and Central Processing Unit (CPU) and Graphical Processing Unit (GPU) chips involves advanced packaging technologies that radically alter traditional design methodologies and flows. Designers of high-speed components are called to co-simulate die, interposers, and package to sign off for their products' signal integrity (SI)… Read More »Signal Integrity Issues for Silicon Interposers
Making Way for Open-Source Hardware
This is a thought leadership piece that highlights the significance of open-source hardware. Tony McDowell (Rapid Silicon) and Adam Taylor (Adiuvo) will discuss the innovations and changes required to bring awareness to open-source. Rapid Silicon's Raptor Design Suite toolchain has already proven that designs can be secure even in an open-source environment. Rapid Silicon The… Read More »Making Way for Open-Source Hardware
Low-Power Verification Using Xcelium Simulation
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on. The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. This webinar will focus… Read More »Low-Power Verification Using Xcelium Simulation
Device Modeling Using Silvaco Utmost IV
In this webinar, Silvaco will present some of the 2022 Baseline enhancements to our Utmost IV Device Modeling tool. We will introduce the Corner and Retargeting Module, the most recent addition to our modeling software platform, and review some of the newest models and technologies where Silvaco’s Utmost IV is a key contributor. The presentation… Read More »Device Modeling Using Silvaco Utmost IV
DesignCon 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesDesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. Three days of education, exhibits, and networking – technical paper sessions, tutorials, industry panels, product demos, expo hall and social functions. Join fellow engineers at DesignCon and cover all aspects… Read More »DesignCon 2023
DVClub Europe: Make Verification Fun Again with Python and cocotb
cocotb is an open source coroutine-based cosimulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. cocotb connects a testbench written in Python with almost all industry-standard simulators. Additionally, cocotb provides a small but powerful framework to efficiently write testcases and run them against a design. cocotb even includes a test runner framework which… Read More »DVClub Europe: Make Verification Fun Again with Python and cocotb
Synopsys VC Formal DPV Virtual Workshop Series
Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Read More »Synopsys VC Formal DPV Virtual Workshop Series
Is your disk space usage out of control using Perforce, GIT, or Subversion (SVN)?
Learn how to gain control of your disk space with the 3-Pronged Smart Storage Strategy Forget the traditional way of managing data storage, let us show you how to optimize workspaces and enable data reuse with the 3-pronged smart storage strategy! Join us on Thursday, February 2nd, to learn how to minimize the disk-space consumption of… Read More »Is your disk space usage out of control using Perforce, GIT, or Subversion (SVN)?
DVClub Europe – Best Conference Papers from 2022
Best Conference Papers from 2022 These papers are selected from DVCon and CadenceLive! in 2022 as being most relevant to the DVClub Europe community. Agenda (GMT) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Lukas Junger, MachineWare GmbH- SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification 12:30 Josue Quiroga, Barcelona Supercomputing Centre (BSC), Spain;… Read More »DVClub Europe – Best Conference Papers from 2022
Synopsys VC Formal DPV Virtual Workshop Series
Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Read More »Synopsys VC Formal DPV Virtual Workshop Series