Synopsys VC Formal DPV Virtual Workshop Series
Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Read More »Synopsys VC Formal DPV Virtual Workshop Series
Is your disk space usage out of control using Perforce, GIT, or Subversion (SVN)?
Learn how to gain control of your disk space with the 3-Pronged Smart Storage Strategy Forget the traditional way of managing data storage, let us show you how to optimize workspaces and enable data reuse with the 3-pronged smart storage strategy! Join us on Thursday, February 2nd, to learn how to minimize the disk-space consumption of… Read More »Is your disk space usage out of control using Perforce, GIT, or Subversion (SVN)?
DVClub Europe – Best Conference Papers from 2022
Best Conference Papers from 2022 These papers are selected from DVCon and CadenceLive! in 2022 as being most relevant to the DVClub Europe community. Agenda (GMT) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Lukas Junger, MachineWare GmbH- SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification 12:30 Josue Quiroga, Barcelona Supercomputing Centre (BSC), Spain;… Read More »DVClub Europe – Best Conference Papers from 2022
Synopsys VC Formal DPV Virtual Workshop Series
Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Read More »Synopsys VC Formal DPV Virtual Workshop Series
Implementing DFT in 2.5/3D designs using Tessent Multi-die software
In the era of more-than-Moore’s law, chip makers are scaling by adopting complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D). There has been progress throughout the semiconductor ecosystem in bringing 2.5D and 3D ICs designs to the mainstream, including design-for-test (DFT). If you are an engineer, DFT manager, CAD director or someone… Read More »Implementing DFT in 2.5/3D designs using Tessent Multi-die software
Webinar: The Rise of the Chiplet
Join us this Thursday, February 9th to talk about The Rise of the Chiplet. Moderated by SemiEngineering’s Brian Bailey, this webinar will dive into the current landscape for chiplet technology, predictions for the coming years, what’s needed for chiplet adoption, and the status and evolution of die-to-die interface standards. Achronix’s Nick Ilyadis, Semico’s Rich Wawrzyniak, and ODSA’s Bapi… Read More »Webinar: The Rise of the Chiplet
Formal Verification for Non-Specialists
Is formal verification ready for general use or do you need a PhD to use it? Larger companies continue to recruit formal PhDs into their verification teams while other less-well-qualified engineers seem reluctant to go beyond simplified formal "apps". So, what is the truth of the matter? Can non-specialist engineers become productive with formal? In this webinar… Read More »Formal Verification for Non-Specialists
International Symposium on Field-Programmable Gate Arrays
Monterey Marriott 350 Calle Principal, Monterey, CA, United StatesThe ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2023, the 31st edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors… Read More »International Symposium on Field-Programmable Gate Arrays
SemIsrael Tech Webinar
13:30 - 14:00 Low Power Design An Effective Path to Low-Power Design The demand for green and energy efficient products is increasing but getting there has never been easy. In this session, we will look at how to design low-power, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL… Read More »SemIsrael Tech Webinar
Removing the Risk from RISC-V using the RISC-V Trace Standard
With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing, with standards now defined for support technologies such as processor trace, which gives developers access to critical insights and forensic capabilities to… Read More »Removing the Risk from RISC-V using the RISC-V Trace Standard
Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
As an active semiconductor foundry, SilTerra requires frequent process and technology development and enhancements, which can result in an increased need for resources and longer time to market. To meet this ongoing challenge, high productivity library optimization and validation are required. In this webinar, we will share the challenges of developing, optimizing, and validating different… Read More »Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
Introduction to UCIe
UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration. The newly formed UCIe Consortium fosters an open chiplet ecosystem by offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between… Read More »Introduction to UCIe