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Experience the Future of Custom Design with Virtuoso Studio

Radisson Blu Outer King Road, Bengaluru, India

With design boundaries constantly stretched and redefined, traditional borders for “custom design” no longer hold. Creative and intelligent solutions are imperative for boosting overall design, simulation, layout, and verification productivity through ever-changing specifications. Join us for this full-day in-person seminar to learn how Cadence is leveraging its expertise to revolutionize custom design on all fronts… Read More »Experience the Future of Custom Design with Virtuoso Studio

Passive Component Synthesis and Optimization for IC Designs

Join us at this webinar to learn more about the Cadence® EMX® Designer, our newly introduced passive component synthesis and optimization solution. In split seconds, the EMX Designer generates very flexible DRC-clean parametric cells of passive devices, such as inductors, transformers, and T-coils. Leveraging the EMX Planar 3D Solver, the industry’s gold-standard electromagnetic modeling engine,… Read More »Passive Component Synthesis and Optimization for IC Designs

MunEDA User Group 2023

Le Meridien No. 38, Songren Rd, Taipei, Taiwan

We are pleased to invite you to the MunEDA Users Group Meeting 2023. MUGM 2023 will take place on May 16th & 17th (Tue/Wed), 2023 in Munich, Germany. The goal of the event is an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions… Read More »MunEDA User Group 2023

Power Integrity Issues and Solutions for Silicon Interposers

Join us on May 17 for the latest 3D-IC webinar series, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated case and in context with the dice instantiated in a 3D-IC device. The presentation will then explore the completed multi-chip design in a system simulation.… Read More »Power Integrity Issues and Solutions for Silicon Interposers

Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications

When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric models to efficiently achieve etch geometries that accurately match microscopy images (e.g., transmission electron microscopy). In this webinar, we present… Read More »Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications

Annual ESDA Membership Meeting & CEO Outlook

Keysight 5301 Stevens Creek Blvd, Building 5, Santa Clara, United States

The evening begins at the Keysight office, Thursday, May 18, at 5:00pm with the ESD Alliance Annual Membership Meeting. You'll get an overview of the past year's activities and discover what's in store for 2023. The meeting flows directly into a Welcome Reception followed by the powerful CEO Outlook. Enjoy a lively, nourishing networking reception that kicks off the CEO Outlook… Read More »Annual ESDA Membership Meeting & CEO Outlook

Embedded Vision Summit 2023

Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United States

The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why attend? It's a First-Rate Program with Powerful Insights into Practical Perceptual AI. Join us for four days of learning—from tutorials to deep-dive days, covering the latest technical insights,… Read More »Embedded Vision Summit 2023

Extending RISC Processors into Flexible Accelerators using ASIP Designer

Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function… Read More »Extending RISC Processors into Flexible Accelerators using ASIP Designer

DENSO discusses Verification of network relay performance using VisualSim

Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. Efficient in-vehicle network development through simulation combining network and ECU hardware and software elements Time Zone: Japan - 3:00 PM (In Japanese) Asia - 3:00… Read More »DENSO discusses Verification of network relay performance using VisualSim

Advancing MRAM Technology with Atomistic Spin Dynamics Simulations

In this event, experts from Martin-Luther-Universitat Halle Wittenberg, University of York, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. Investigating the potential of novel magnetic tunnel junction (MTJ) materials… Read More »Advancing MRAM Technology with Atomistic Spin Dynamics Simulations

Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions

Synopsys Webinar | Wednesday, May 24, 2023 | 10:00 - 10:45 a.m. IST Engineering resources are getting stretched thinner and thinner as design complexity increases. Automation is a significant driver to help engineers overcome resource constraints and meet critical time-to-market windows. Two of the top three challenges cited by the engineering community in a recent… Read More »Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions