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Extending RISC Processors into Flexible Accelerators using ASIP Designer

May 24, 2023 @ 8:00 am - 10:00 am PDT

Synopsys, May 24, 2023
Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications

The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline, compatibility with and reuse of existing processor ecosystem elements is facilitated.

Synopsys ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology, the ISA and microarchitecture can be tuned quickly to the application domain.

This seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study by Lund University shows the design exploration for a RISC-V based VLIW processor for feature extraction in smart vision systems, using ASIP Designer. The second case study by Synopsys shows an ASIP for post-quantum cryptography. A RISC-V baseline architecture is gradually extended into an ASIP that is optimized for the Kyber encryption mechanism but accelerating also other cryptographic applications.


Who Should Attend?

If you are a design engineer, algorithm developer, software engineer, system architect, or design manager focusing on advanced SoCs requiring application-specific optimizations, you won’t want to miss this event.


An Introduction to Domain-Specific Processors and ASIP Designer

Patrick Verbist, Sr. Product Manager, Synopsys Belgium

Falco Munsche, Technical Marketing Manager, Synopsys Germany

08:00am – 8:50am PT

Domain-specific processors (also referred to as Application-specific processors, ASIP) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs and will provide an overview of Synopsys’ ASIP Designer tool-suite.

Case study: Energy-Efficient Application-Specific Instruction Set Processor for Feature Extraction in Smart Vision Systems

Lucas Ferreira, PhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department, Lund University

8:50am – 9:20am PT

In computer-vision feature extraction algorithms, compressing the image into a sparse set of trackable keypoints, empowers navigation-critical systems such as Simultaneous Localization and Mapping (SLAM) in autonomous robots, and also other applications such as augmented reality and 3D reconstruction. Most of those applications are performed in battery-powered gadgets featuring in common a very stringent power-budget. Near-to-sensor computing of feature extraction algorithms allows for several design optimizations. First, the overall on-chip memory requirements can be lessened, and second, the internal data movement can be minimized. This work explores the usage of an Application Specific Instruction Set Processor (ASIP), designed with Synopsys ASIP Designer, optimized for performing feature extraction in a real-time and energy-efficient manner. The ASIP features a Very Long Instruction Word (VLIW) architecture comprising one RV32I RISC-V and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. Oriented FAST and Rotated BRIEF (ORB) is thoroughly explored to validate the proposed architecture, achieving a throughput of 140 Frames-Per-Second (FPS) for VGA images for one scale, while reducing the number of memory accesses by 2 orders of magnitude as compared to other embedded general-purpose architectures.

Case study: An ASIP for Post-Quantum Cryptography

Falco Munsche, Technical Marketing Manager, Synopsys Germany

9:20am –10:00am PT

Kyber, the first standardized key encryption mechanism designed to withstand attacks with future powerful quantum computers, is computationally very demanding due to extensive use of hashing, for example. In this case study, an ASIP optimized for accelerating Kyber was developed, starting from an open-source implementation compiled and profiled on a RISC-V base model, gradually adding architectural specializations that go beyond simple RISC-V extension mechanisms. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround, using the compiler-in-the-loop and synthesis-in-the-loop optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step.

Meet The Speakers

Patrick Verbist

Sr. Product Manager


Patrick Verbist is the Product Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and, prior to the acquisition by Synopsys in 2014, Director of Sales at Target Compiler Technologies. Before Target, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven, Belgium.

Falco Munsche

Technical Marketing Manager


Falco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP Design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys.

He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University.

Lucas Ferreira

PhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department

Lund University

Lucas Ferreira was born in São Paulo, Brazil, 1993. He received his bachelors both in Science and Technology, and Automation and Control Engineering respectively at Federal University of ABC 2015-2017 (São Paulo). In 2019 he received his M.Sc. degree in Embedded Electronics from Lund University.

Since May 2019, he is working at the department of Electrical and Information Technology, Lund University as a doctoral candidate. His main focus of research is on domain-specific processor design with focus on computer vision, machine learning, and autonomous drones.


May 24, 2023
8:00 am - 10:00 am PDT
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