FPGA Conference Europe 2023
NH München Ost Conference Center Einsteinring 20, Munich, Aschheim, GermanyFPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the… Read More »FPGA Conference Europe 2023
Free Silicon Conference – FSiC2023
Sorbonne Université 15-21 Rue de l'École de Médecine, Paris, FranceThe 2023 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on July 10,11,12 2023 (Monday to Wednesday). This event will build on top of the past FSiC2019 and FSiC2022 editions. The conference will connect… Read More »Free Silicon Conference – FSiC2023
Embedded UVM (eUVM)
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 11th July with a theme of "Embedded UVM(eUVM)". Introduction to Embedded UVM to enable HPC-Powered UVM Testbenches with… Read More »Embedded UVM (eUVM)
An AI/ML Driven High-Level Synthesis Solution
High-Level Synthesis (HLS) tools yield better PPA when the "right set" of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and… Read More »An AI/ML Driven High-Level Synthesis Solution
Comprehensive Static Verification for FPGA and ASIC RTL Designers
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in… Read More »Comprehensive Static Verification for FPGA and ASIC RTL Designers
Rambus Design Summit 2023
Back for its fourth year, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center, AI/ML, automotive and… Read More »Rambus Design Summit 2023
Key MAC Considerations for the Road to 1.6T Ethernet Success
224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations, challenges and solutions designers need to know for the MAC… Read More »Key MAC Considerations for the Road to 1.6T Ethernet Success
Automated Verification for Cache Coherent RISC-V SoCs
RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification… Read More »Automated Verification for Cache Coherent RISC-V SoCs
Achieve Optimal PPA Targets Using AI-Driven Technology
Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power, performance, and area (PPA). Manual methods are no longer viable given shrinking market… Read More »Achieve Optimal PPA Targets Using AI-Driven Technology
3D-IC Foundry Frameworks
Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC, Samsung, and Intel and how Ansys simulation tools and… Read More »3D-IC Foundry Frameworks
Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc.,… Read More »Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
International Test Conference – India, 2023
Radisson Blu Outer King Road, Bengaluru, IndiaInternational Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test,… Read More »International Test Conference – India, 2023