ERI 2.0 Summit
Hyatt Regency Seattle 805 Howell Street, Seattle, WA, United StatesWatch as leaders from our government agencies, the Defense Industrial Base, and prestigious universities bring unique and indispensable perspectives on our domestic semiconductor industry, national and economic security, and future… Read More »ERI 2.0 Summit
Virtuoso Studio and Signoff Technology Day
Cadence Design Systems, Building 5 2655 Seely Avenue, San Jose, CA, United StatesJoin us at CadenceCONNECT™: Virtuoso Studio and Signoff Technology Day focusing on our latest technology within the new Cadence® Virtuoso® Studio. Date: Thursday, August 24, 2023 Time: 8:30am – 5:00pm… Read More »Virtuoso Studio and Signoff Technology Day
Hot Chips 2023
Stanford University 471 Lagunita Drive, Stanford, CA, United StatesHot Chips 2023 (advance program) will be held as a hybrid conference with in-person attendance at Stanford University from August 27 to 29, 2023. Conference Format Hot Chips 2023 will… Read More »Hot Chips 2023
GlobalFoundries Technology Summit 2023
San Jose Marriott 301 S Market Street, San Jose, CA, United StatesRegister now and join us at GlobalFoundries Technology Summit 2023! GF Technology Summit (GTS) 2023 is our worldwide, annual series of technology-focused events. GTS brings together leaders from the commercial, business and… Read More »GlobalFoundries Technology Summit 2023
High-Speed Channel Signal Integrity Optimization
Join our webinar as we share new optimization techniques to improve the efficiency and performance of your designs. The Optimality™ Explorer in the the Clarity™ 3D workbench allows users to… Read More »High-Speed Channel Signal Integrity Optimization
UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard… Read More »UCIe-Based Chiplet Verification – from IP to SoC
Four Important Signal Integrity Principles Demonstrated with Virtual Prototypes
Signal integrity encompasses all the problems that arise when interconnects are not electrically transparent. One difficulty in understanding signal integrity principles is that these effects can't be seen, felt, or… Read More »Four Important Signal Integrity Principles Demonstrated with Virtual Prototypes
Accelerating Mainstream Adoption of Multi-Die Systems
Synopsys recently hosted a panel discussion with Ansys, Bosch, Intel, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast… Read More »Accelerating Mainstream Adoption of Multi-Die Systems
Advanced Testbench for a Complex DUT
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach… Read More »Advanced Testbench for a Complex DUT
Advanced Testbench for a Complex DUT
Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on… Read More »Advanced Testbench for a Complex DUT
IEEE SOCC 2023
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesSoCs and SiPs for Edge Intelligence and Accelerated Computing System-on-Chip (SoC) and System-in-Package (SiP) devices, comprising digital, analog, optical, RF, and Micro-Electro-Mechanical Systems (MEMS) are foundations of ubiquitous embedded high-performance computing (HPC). Such… Read More »IEEE SOCC 2023
Real Intent Static Sign-Off Seminar in Israel
VERT Lagoon Netanya, IsraelTime Topic Speaker 09:15 – 09:45 Check-in and light breakfast 09:45 – 10:00 Introduction of Real Intent and speakers Uri Farkash, Real Intent – Senior Sales Director 10:00 – 10:30… Read More »Real Intent Static Sign-Off Seminar in Israel