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ISTFA 2023
Phoenix Convention Center 100 North Third Street, Phoenix, AZ, United StatesSaving global resources by increasing energy efficiency is among the most significant problems that global society must address today. To achieve this, a major target is developing efficient and reliable… ISTFA 2023
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CadenceCONNECT: The Race Is On!
Cadence San Jose, CA, United StatesEvent Overview Date: Monday, November 13, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand for advanced-node chip design that… CadenceCONNECT: The Race Is On!
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PCB Design Best Practices: Design Automation
re you harnessing the full power of your PCB design software? In this live discussion, experts Stephen Chavez and Ray Macias will discuss the benefits of using PCB design automation, and… PCB Design Best Practices: Design Automation
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DVCon Europe 2023
Holiday Inn Munich - City Centre Hochstraße 3, Munich, GermanyThe Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation and integration. It is a place where the… DVCon Europe 2023
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Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will… Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
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Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful webinar on how you too… Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
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Why Chiplets with UCIe are the Next Big Thing
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an… Why Chiplets with UCIe are the Next Big Thing
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Fail-safe Electronics for Automotive
I would like to invite you to attend our upcoming webinar on Wednesday, November 15 at 8 a.m. PST. This 1-hour panel will feature SoC experts from CARIAD, Infineon, NXP… Fail-safe Electronics for Automotive
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TSMC 2023 Open Innovation Platform Ecosystem Forum – China
Shangri-La Nanjing Hotel 29 Zhongyang Road, Gulou District, Nanjing, ChinaJoin us at the TSMC 2023 China OIP Ecosystem Forum! China OIP Ecosystem Forum (In-Person Event) Date: November 15, 2023 (Wednesday) Time: 9:30a.m. - 5:45p.m. Venue: Shangri-La Nanjing Hotel 329 Zhongyang Road, Gulou… TSMC 2023 Open Innovation Platform Ecosystem Forum – China
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Achieve 95% Accurate Power Measurement during Architectural Exploration
Are you in the conceptualization and architectural exploration phases, where assessing the power budget is of paramount importance? If you're looking to achieve precise power measurement for critical aspects like… Achieve 95% Accurate Power Measurement during Architectural Exploration
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ASIP University Day 2023
ASIP University Day: Domain-Specific Processor Design using ASIP Designer Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP… ASIP University Day 2023
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ParagonX – Intelligent analysis, visualization and debugging tool for IC layout parasitics
I would like to invite you to Ansys Paragon X webinar that we are hosting on Wednesday, November 15th 17:00 PM (Israel time). ParagonX intended for analyzing, simulating, debugging, visualizing,… ParagonX – Intelligent analysis, visualization and debugging tool for IC layout parasitics
12 events found.