Open Source Summit – North America
Seattle Convention Center 900 Pine Street, Seattle, WA, United StatesRegistration Cost: $15 This half day program will Introduce the audience to the many aspects of open source hardware and software development, and how it is helping the industry to accelerate beyond what Moore’s law has predicted. Talks will cover numerous aspects of hardware / software development and provide motivation to learn more about the challenges… Read More »Open Source Summit – North America
Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process. Learn how the latest innovations in QuestaSim address these challenges by enabling full off-line… Read More »Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
DVClub India – Ensuring my Design Verification is ISO26262 Compliant
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaTBD
CS Inernational Conference
Sheraton Brussels Airport Hotel Brussels, Belgiumhe 14th CS International builds on the strengths of its predecessors, with around 40 leaders from industry and academia delivering presentations that fall within five key themes: Ensuring SiC’s Phenomenal Success; Expanding Horizons for Surface Emitters; Accelerating the Growth of GaN; Taking Power from the Photon; and New Frontiers for the LED. Those attending these… Read More »CS Inernational Conference
Streamline MMIC Design Efficiency with Intelligent Design Data Management
In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and RF components? Wondering about the automatic synchronization of schematics and layouts across various electronic design automation (EDA) tools? Trusted by hundreds of IC design organizations… Read More »Streamline MMIC Design Efficiency with Intelligent Design Data Management
Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the… Read More »Exploring the Advancement of Chiplet Technology and the Ecosystem
CadenceLIVE Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings users, developers, and industry experts together to connect, share ideas, and inspire design creativity. Attendees have the opportunity… Read More »CadenceLIVE Silicon Valley 2024
Introduction to ParagonX
Are you ready to supercharge your design process? Introducing our Diakopto Training Program - your gateway to a faster, easier, and more intuitive approach to design analysis and optimization! In this course, you'll learn how to: Analyze and visualize layout parasitics with precision using R/C/delay/I maps. Perform net matching for accurate and refined designs. Identify… Read More »Introduction to ParagonX
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Latch-Up 2024: Boston
Massachusetts Institute of Technology 77 Massachusetts Avenue, Boston, MA, United StatesFriday to Sunday April 19–21, 2024 in Boston, MA, USA The Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event for the open source digital design community, much like its European sister conference ORConf, run by the FOSSi Foundation. You are all invited! The FOSSi… Read More »Latch-Up 2024: Boston
CICC 2024
DoubleTree by Hilton Denver 3203 Quebec Street, Denver, CO, United StatesThe IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design… Read More »CICC 2024