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An AI/ML Driven High-Level Synthesis Solution
High-Level Synthesis (HLS) tools yield better PPA when the "right set" of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and… An AI/ML Driven High-Level Synthesis Solution
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Comprehensive Static Verification for FPGA and ASIC RTL Designers
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in… Comprehensive Static Verification for FPGA and ASIC RTL Designers
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Rambus Design Summit 2023
Back for its fourth year, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center, AI/ML, automotive and… Rambus Design Summit 2023
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Key MAC Considerations for the Road to 1.6T Ethernet Success
224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations, challenges and solutions designers need to know for the MAC… Key MAC Considerations for the Road to 1.6T Ethernet Success
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Automated Verification for Cache Coherent RISC-V SoCs
RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification… Automated Verification for Cache Coherent RISC-V SoCs
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Achieve Optimal PPA Targets Using AI-Driven Technology
Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power, performance, and area (PPA). Manual methods are no longer viable given shrinking market… Achieve Optimal PPA Targets Using AI-Driven Technology
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3D-IC Foundry Frameworks
Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC, Samsung, and Intel and how Ansys simulation tools and… 3D-IC Foundry Frameworks
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Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc.,… Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
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International Test Conference – India, 2023
Radisson Blu Outer King Road, Bengaluru, IndiaInternational Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test,… International Test Conference – India, 2023
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ITC India 2023
Hotel Radisson Blu Marathalli ORR, Bengaluru, IndiaKeynote speakers Fadi Maamari VP of Engineering at Synopsys Sule Ozev Arizona State University About Us International Test Conference is the world’s premier venue dedicated to the electronic test of… ITC India 2023
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Solution for 3D-IC Interposer Signal Integrity
Our upcoming CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity is designed to teach engineers to translate a GDSII stream format (GDSII) file and partition it into simulation blocks for the… Solution for 3D-IC Interposer Signal Integrity
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Solution for 3D-IC Interposer Signal Integrity
3D-IC design requires early analysis of thermal properties, power delivery, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow… Solution for 3D-IC Interposer Signal Integrity
12 events found.