-
-
Python in Verification, Online Meetup
At Veriest, we believe in knowledge sharing. In our recent meetup events, hundreds of professionals from 20+ different countries gathered to listen to different industry experts from companies such as Intel, ST Microelectronics, arm, Texas Instruments, Nvidia and more. This time, we'll focus on the polemic topic of using Python in Verification. We'll have two presentations, both… Python in Verification, Online Meetup
-
Semiconductor Device Improvement Using Atomera MST Technologies and MSTcad Toolset.
Join our webinar to learn about how Atomera’s MSTcad™ toolset can be used to model and optimize transistor performance when integrating Atomera’s Mears Silicon Technology™ (MST) into a semiconductor process. Topics covered include how MST® enhances most transistor characteristics, and how the MSTcad toolset provides sophisticated modeling capabilities for analyzing MST’s dopant blocking capabilities, how users… Semiconductor Device Improvement Using Atomera MST Technologies and MSTcad Toolset.
-
IMAPS Device Packaging
We-Ko-Pa Resort & Conference Center 10438 Wekopa Way, Fort McDowell, AZ, United StatesThe 18th Annual Device Packaging Conference (DPC 2022) will be held at the WeKoPa Resort and Conference Center, from March 7-10, 2022. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS). The conference is a major forum for the exchange of knowledge and provides numerous technical, social and networking opportunities for meeting leading experts in… IMAPS Device Packaging
-
Introduction to the Joules RTL Power Solution
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar. Built on a multi-threaded frame-based architecture, the Cadence® Joules™ RTL Power Solution delivers 20X faster time-based RTL power… Introduction to the Joules RTL Power Solution
-
EE Times: Advanced Automotive Tech Forum
In the last year, the evolution towards electric vehicles accelerated faster than anticipated. Autonomous driving technology has already been pushed from a short-term priority to a long-term goal, but the race to be first with AVs remains fierce. Meanwhile, there seems to be a shift in priorities from driver-assist technologies toward driver monitoring systems. The… EE Times: Advanced Automotive Tech Forum
-
Methodics User Group
An event driven platform for managing the design lifecycle is considered the holy grail for many semiconductor enterprises. It can enable DevOps automation and optimize many of the manual processes that affect team productivity. Although some tools try to use triggers to track important metadata during the design process, Methodics IPLM is taking a different… Methodics User Group
-
Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
Complex bus protocols, increased on-chip functionalities, coupled with limited shared I/O resources, result in complex wiring connections in SoCs with numerous muxing schemes. Simulation and structural analysis approaches require huge effort and may lead to bug escapes making them inefficient for SoC connectivity verification. Connectivity verification using formal techniques is exhaustive and helps making… Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
-
CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and… CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
-
Spatial Audio: What it is and how to overcome its unique challenges to provide a complete solution
Audiovisual experiences in XR, gaming, movies, and concerts can all be enhanced with spatial audio experience immersive technology. A superior spatial audio experience occurs when you combine headphones, with wearable head tracking, and on-device processing. Believe it or not, despite the recent wide adoption of Spatial/3D Audio, the concept and technology have been around for a… Spatial Audio: What it is and how to overcome its unique challenges to provide a complete solution
-
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar… Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
-
How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV
In this webinar we will examine some of the key features and advantages of Utmost IV for device modeling and characterization, and the major design flows where Utmost IV is a key component. We will also present the latest product enhancements and introduce the new Utmost IV Corner and Retargeting Module. To conclude, we will… How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV
-
Power Intent Management for Large SoCs
Defacto Techologie 2 rue Emile Augier, Grenoble, FranceThe complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area), it's challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers. During this… Power Intent Management for Large SoCs
12 events found.