-
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar… Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
-
How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV
In this webinar we will examine some of the key features and advantages of Utmost IV for device modeling and characterization, and the major design flows where Utmost IV is a key component. We will also present the latest product enhancements and introduce the new Utmost IV Corner and Retargeting Module. To conclude, we will… How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV
-
Power Intent Management for Large SoCs
Defacto Techologie 2 rue Emile Augier, Grenoble, FranceThe complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area), it's challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers. During this… Power Intent Management for Large SoCs
-
Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification techniques such as constrained random verification with assertion-based verification (ABV) can be used to help identify ambiguous or incomplete requirements early in the design and… Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
-
2021 ESD Alliance | IEEE CEDA Phil Kaufman Award
The GlassHouse 2 S Market Street, San Jose, CA, United StatesThe Electronic System Design Alliance and The IEEE Council on EDA (CEDA) are proud to honor DR. ANIRUDH DEVGAN President and CEO of Cadence Design Systems with the 2021 Phil Kaufman Award Dr. Devgan is being honored for his extensive contributions to electronic design automation (EDA). He is widely recognized as a leading authority in… 2021 ESD Alliance | IEEE CEDA Phil Kaufman Award
-
DATE 2022
Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test DATE conference is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a… DATE 2022
-
Memory Bandwidth Races Higher with HBM3
With the formal release of the HBM3 specification, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers… Memory Bandwidth Races Higher with HBM3
-
Using ST Stellar MCU Virtual Prototypes to Deliver Next-Generation Software-Defined Vehicles
Automotive microcontrollers for next-generation software-defined vehicles need to deliver higher software capabilities. ST Stellar Integration MCUs offer safe, secure, and deterministic solutions for new vehicle architectures. The use of virtual prototypes is a key enabler to solving the emerging, complex software development challenges throughout the automotive design and test supply chain, such as feature integration,… Using ST Stellar MCU Virtual Prototypes to Deliver Next-Generation Software-Defined Vehicles
-
Analog Fault Injection Simplifies ISO 26262 Compliance
As the automotive market moves toward electrified drivetrains and autonomous driving systems, chip makers increasingly need to design integrated mixed-signal chips that meet the ISO 26262 automotive certification. With these complex designs, designers will require automation to overcome the limits of using expert judgment to ensure compliance. Integrating functional safety analysis into their existing design… Analog Fault Injection Simplifies ISO 26262 Compliance
-
How Silvaco TCAD is at the Heart of Innovation in RF Devices
At high frequency, the accurate modeling of parasitic elements is crucial to IC design. Substrate behavior is a significant contributor to such parasitics, and its modelling is a challenge, not only under small-signal conditions due to strongly non-uniform resistivity profiles in semiconductor materials, but especially under large-amplitude excitations. In this work, Silvaco’s TCAD Victory Device… How Silvaco TCAD is at the Heart of Innovation in RF Devices
-
What’s New in Clarity 2022.1
The Cadence® Clarity™ 3D Solver, utilized by scores of customers across the globe, continues to accelerate design flows for leading companies in industries such as medical, hyperscale computing, 5G, automotive, and industrial internet of things (IIoT). The latest 2022.1 release continues to widen the gap between the Clarity 3D finite element (FEM) solver and alternatives in both… What’s New in Clarity 2022.1
-
GOMACTech 2022
Hyatt Regecy Miami 400 South East Second Avenue, Miami, FL, United StatesWELCOME TO GOMACTech 2022 Enabling Distributed Capabilities: Microelectronics Thriving in the Face of Change GOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce… GOMACTech 2022
12 events found.