-
5X Faster Equivalence Checking with Formality ML-driven DPX
Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation from production quality Equivalence checking is to be able to complete verification with minimal efforts and the fastest turn-around-time. This presentation… 5X Faster Equivalence Checking with Formality ML-driven DPX
-
Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach. Creating a verification component (VC)… Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
-
2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY AND CIRCUITS
Hilton Hawaiian Village 2005 Kālia Rd, Honolulu, HI, United StatesIn-person with on-demand content The 2022 IEEE Symposium on VLSI Technology and Circuits will be organized as a hybrid event with both live sessions on-site in the Hilton Hawaiian Village to enable networking opportunities, and on-demand sessions to allow access to selected talks and panels to those who cannot travel. The five-day event will include:… 2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY AND CIRCUITS
-
ASYNC 2022 Summer School: Gate-level Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using… ASYNC 2022 Summer School: Gate-level Design
-
Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, disjointed design tools and flows provide a serious risk for product… Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
-
How Static and Dynamic IR Drop Analysis Can Help PCB Designs Challenges
As boards become smaller and faster, the environment for thermal issues becomes increasingly challenging. The thermal management of significant resistive losses in PCB and package structures is critical, especially because these resistive losses are also temperature-dependent, making dynamic and static IR drop analysis crucial in addressing the performance and capacity challenges of such designs. Join… How Static and Dynamic IR Drop Analysis Can Help PCB Designs Challenges
-
Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
Electronic systems in automobiles are growing rapidly in size, complexity, and critical functionality. As a result, functional safety verification is emerging as an essential requirement for automotive SoC and IP designs. In order to assure that even the most stringent safety standards are met at a faster pace, comprehensive and fast fault injection and simulation… Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
-
Debugging Features of UVM
A UVM testbench is a large and complex piece of software. At some stage, like any other large and complex piece of software, a verification environment written using UVM is going to require debugging. There are various debugging features built into UVM to help with this. In this webinar, Doulos Senior Member Technical Staff, Doug… Debugging Features of UVM
-
TSMC 2022 Technology Symposium – North America
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesA Technology Symposium (In-Person Event) Date: June 16, 2022 (Thursday) Time: 8:30a.m. - 5:05p.m. Venue: Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA 95054 NA Technology Symposium (Online VOD Event) Date: June 30, 2022 (Thursday) Website link to be announced in June Get the latest on: TSMC's smartphone, HPC, IoT, and automotive… TSMC 2022 Technology Symposium – North America
-
Large-Scale and Accurate Density Functional Theory (DFT) Simulations with QuantumATK
Join this Synopsys webinar to learn how to perform large-scale, accurate and reliable Density Functional Theory (DFT) simulations with the QuantumATK platform: Discover how to perform accurate and reliable large scale DFT simulations even at the hybrid functional level - with Linear Combination of Atomic Orbital basis set using modest computational resources. Learn how to… Large-Scale and Accurate Density Functional Theory (DFT) Simulations with QuantumATK
-
Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, disjointed design tools and flows create a serious risk of product… Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
-
OSVVM’s Test Reports and Simulator Independent Scripting
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay… OSVVM’s Test Reports and Simulator Independent Scripting
12 events found.