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CMOS Circuit Techniques for Wireline Transmitters Part I
Synopsys Webinar – Part I In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part I
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CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
Google 237 Moffett Park Drive, Sunnyvale, CA, United StatesIP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side, the concept of package managers is widely used to build a product from many different sources, but chip designers often rely on ad-hoc solutions which tends to build up… CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
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Ways to run cocotb: makefiles, cocotb-test, or your custom setup
cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec's Riviera-PRO and executes Python testbenches in that context. In this webinar, we will look at ways to invoke your simulator of choice in a way that also starts with cocotb. We will show ways to extend the setup to… Ways to run cocotb: makefiles, cocotb-test, or your custom setup
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Elevating Consumer Electronics Design Through Cloud-Based Simulation
Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. Sign up for this webinar to learn more about designing better consumer electronics products thanks to simulation in the cloud. About this Webinar Consumer electronic devices are part of our daily lives and include phones,… Elevating Consumer Electronics Design Through Cloud-Based Simulation
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Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
Join industry experts from aerospace, government, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI), highlighting some of the technological, manufacturing, and economic complexities as well as security, reliability, and safety challenges. The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research… Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
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ISTFA 2023
Phoenix Convention Center 100 North Third Street, Phoenix, AZ, United StatesSaving global resources by increasing energy efficiency is among the most significant problems that global society must address today. To achieve this, a major target is developing efficient and reliable power electronics devices for providing the required high-performing hardware components. Power semiconductors based on silicon carbide (SiC) and gallium nitride (GaN) technologies are becoming increasingly… ISTFA 2023
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CadenceCONNECT: The Race Is On!
Cadence San Jose, CA, United StatesEvent Overview Date: Monday, November 13, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design.… CadenceCONNECT: The Race Is On!
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PCB Design Best Practices: Design Automation
re you harnessing the full power of your PCB design software? In this live discussion, experts Stephen Chavez and Ray Macias will discuss the benefits of using PCB design automation, and show how certain capabilities such as component placement, trace routing, and generating manufacturing outputs to include intelligent data formats can improve your design cycle times. They’ll offer… PCB Design Best Practices: Design Automation
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DVCon Europe 2023
Holiday Inn Munich - City Centre Hochstraße 3, Munich, GermanyThe Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation and integration. It is a place where the latest methodologies and technologies of tools, languages, and standards for integrated and embedded systems and products are shared and discussed. Applications of interest include (but… DVCon Europe 2023
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Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints Manager relative to manual time-consuming approaches. We will… Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
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Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software, this webinar will offer key insights into… Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
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Why Chiplets with UCIe are the Next Big Thing
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an open industry standard, to communicate with each other. Combined in a Systems-on-Package (SoP), they provide superior performance, reduced power consumption, and increased design flexibility for customized applications… Why Chiplets with UCIe are the Next Big Thing
12 events found.