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Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
The Cadence® AWR® V16 for RF Design Excellence Webinar Series introduces the latest capabilities in Cadence® AWR Design Environment® Version 16 (V16), providing ready access to Cadence Clarity™ 3D Solver and Celsius™ Thermal Solver for unconstrained capacity to solve large-scale and complex RF systems directly from within the RF design platform. Our next webinar in… Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
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Python in Verification Online Meetup
Veriest is inviting you to another event in our series of online Verification Meetups. This time, we'll have two presentations on the polemic topic of using Python in Verification, one by an industry expert and the other by one of Veriest technical leaders. Save the date and watch this space for more details!
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Linley Fall Processor Conference 2021
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesFor more than a decade, The Linley Group has delivered the industry’s premier processor conferences. This year, the Linley Fall Processor Conference will return to Santa Clara on October 20-21, 2021. If you can’t attend in person, attend the virtual event on October 27-29 and November 3-5 with live Q&A and breakout sessions. Please stay… Linley Fall Processor Conference 2021
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VSDOpen 2021 Online Conference
What is VSDOpen 2021 Agenda? Key strategy - Provide High Tech Experience of developing analog designs using Open-Source Tools, PDKs and Cloud Platform 3 days of Conference Tutorials Key Focus – Analog Products, Open-source FPGA and Semiconductor IP's Keynote Speaker – Industry leaders focused on Developing IoT, 5G and AI products, Professor from open-source Research… VSDOpen 2021 Online Conference
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Role of MIPI IP in New Automotive SoC Architectures
SoCs for Automotive applications such as ADAS, Infotainment, and connected vehicles are shifting to a more domain-based architecture. As a result, the car’s electronics for such applications are requiring a major redesign for a more efficient connectivity with the utmost reliability, security, and safety. This shift along with the increasing use of sensors and displays… Role of MIPI IP in New Automotive SoC Architectures
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CadenceCONNECT – Mission Critical 2021
Overview CadenceCONNECT will introduce you to optimized design methodologies for mission-critical electronics system applications like A&D, safety, security, 5G, and others. The event brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification, and discovering new techniques for designing advanced silicon, SoCs, and systems. Keynote 10:00… CadenceCONNECT – Mission Critical 2021
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Compare Performance-power of Arm Cortex vs RISC-V for AI applications
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1, SiFive u74, and other vendor cores. Aside from the processor resources such as cache and memory, the… Compare Performance-power of Arm Cortex vs RISC-V for AI applications
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Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement… Using OVL for Assertion-based Verification of Verilog and VHDL Designs
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Wafers to Wall Street—A Semiconductor Outlook: Emerging Markets & Technologies Driving Significant Investment Globally
Major investments are developing in semiconductor fab capacity expansion globally and North America. Join industry colleagues online Friday, October 22, for a thought-provoking, VIRTUAL forum on the outlook, competitive environment, market, and technology trends driving fab expansion investment in the semiconductor industry. The discussion includes an analysis of the opportunities and challenges presented by end market drivers. Hear… Wafers to Wall Street—A Semiconductor Outlook: Emerging Markets & Technologies Driving Significant Investment Globally
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DVCon Europe 2021
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques,… DVCon Europe 2021
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TSMC 2021 Online OIP Ecosystem Forum
The TSMC OIP Ecosystem Forum brings together TSMC's design ecosystem partners and customers to share practical, tested solutions to today's design challenges. More than 95% of last year's event attendees found that the Forum helped them better understand TSMC's Open Innovation Platform and found it insightful to hear directly from TSMC OIP member companies. This… TSMC 2021 Online OIP Ecosystem Forum
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Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
For the past 10+ years, semiconductor design has moved from a project-based "start again" mindset to a more modular, "IP-centric" approach. This has significantly reduced project cost and improved time-to-market by encouraging the outsourcing of niche areas of the design to specialists, enabling the use of foundry sourced IP (often for free) and emphasizing the… Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
12 events found.