20th International Conference on IC Design and Technology (ICICDT)
University of Tokyo 7 Chome-3-1 Hongo, Tokyo, Japan2023 ICICDT is the twentieth edition (20th) in the series of the International Conference on IC Design and Technology, organized since 2004. 2023 ICICDT will be co-organized and held at… Read More »20th International Conference on IC Design and Technology (ICICDT)
Unleashing Innovation with UCIe
Exploring the Next Frontier in Chip Integration Webinar Agenda : Introduction to all UCIe layers Decrypting FLITs, PHY Trainings, Bring up flows FDI-RDI , main band and side band FLIT… Read More »Unleashing Innovation with UCIe
GTS 2023 – Munich
Sofitel Munich Bayerpost Bayerstrasse 12, Munich, GermanyRegister now and join us at GlobalFoundries Technology Summit 2023! GF Technology Summit (GTS) 2023 is our worldwide, annual series of technology-focused events. GTS brings together leaders from the commercial, business and… Read More »GTS 2023 – Munich
Synopsys VSO.ai Virtual Workshop
Virtual workshop with hands-on labs Achieving coverage closure continues to remain a challenge for customers and there is a growing need for a system to work autonomously to reach the… Read More »Synopsys VSO.ai Virtual Workshop
TSMC 2023 North America OIP Ecosystem Forum
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and… Read More »TSMC 2023 North America OIP Ecosystem Forum
Cadence Training: Cerebrus Intelligent Chip Explorer
Please join me, Cadence Training and Application Engineer Krishna Atreya, for this free technical Training Webinar. What Is the Webinar About? The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary,… Read More »Cadence Training: Cerebrus Intelligent Chip Explorer
Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from… Read More »Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
FPGA Design Verification – Advanced Testbench Implementation
Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design… Read More »FPGA Design Verification – Advanced Testbench Implementation
56th International Microelectronics Assembly and Packaging Society (IMAPS)
This packed conference brings together industry engineers, researchers and top experts involved in advanced packaging and microelectronics assembly. IMAPS Symposium offers a robust technical program with 5 concurrent tracks and 100+… Read More »56th International Microelectronics Assembly and Packaging Society (IMAPS)
TSMC 2023 Europe OIP Ecosystem Forum
Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701 Amsterdam, Amsterdam, NetherlandsLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and… Read More »TSMC 2023 Europe OIP Ecosystem Forum
Verisium Debug for UVM Testbench
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the… Read More »Verisium Debug for UVM Testbench
EDPS 2023
Synopsys Building 1 800 North Mary Avenue, Sunnyvale, CA, United StatesEDPS 2023 is approaching fast! The program is firming up - please see the program page for a preliminary list of talks. REGISTRATION IS NOW OPEN. Everyone, including speakers, must register. 2023-ieee-edps.eventbrite.com… Read More »EDPS 2023