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The Must Attend Event for Chip, Board, and Systems Design Engineers DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. 40 Under 40 Calling all Emerging Engineers and Leaders! DesignCon’s 40 Under 40 program launches in 2024 and provides… DesignCon 2024 |
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Dear SIPI Engineer, As a member of the engineering community, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. This event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will… Signal & Power Integrity Special Interest Group |
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4 events,
The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions of the experts,… Chiplet Summit
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Help build Canada's role in North America's integrated semiconductor supply chain. Featuring key industry and government decision-makers from Canada, the United States, and international jurisdictions, your insights at this by-invitation-only event will help us build an effective action plan. The summit will establish priorities and define opportunities to accelerate the growth, development, and competitiveness of… Canada’s Semiconductor Summit
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In a world of increasing trust and assurance challenges for microelectronic devices, emerging industry standards and defense policy demand early and advanced functional verification methods before ICs may be deployed in critical end products and systems. Questa technologies, built upon a foundation of world-class simulation and formal engines, provide the results desired for raising and meeting higher levels… Functional Verification workflow for Trusted and Assured Microelectronics
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Hardware designs intended for the automotive domain need to implement safety mechanisms to minimize the risk of accidents and injuries caused by hardware-related issues in vehicles. In this DVClub we will cover how those safety mechanisms need to be verified to be compliant with ISO26262, the international standard covering automotive safety. Agenda (GMT) 12:00 Welcome… DVClub Europe: Verifying Safety in Automotive |
3 events,
Join Cadence in person for the 8th annual CadenceCONNECT Photonics event and workshop on February 7 – 8, 2024, to discuss the increasingly important role of photonics in enabling AI transformation. We all know photonics is essential for communication, but how about computing? What are its advantages and challenges? Which applications are best suited? How… CadenceCONNECT – Photonics Event
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Join us for this webinar on RF GaN amplifier design using electromagnetic/thermal 3D solvers. We will discuss the step-by-step process of building a GaN amplifier, beginning with the transistor model in the circuit simulator. The webinar will outline the steps required to convert this to a physical layout for electromagnetic simulation and verification while integrating… Design Exploration of RF GaN Amplifier, 3D Packaging, and Thermal Analysis |
4 events,
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We start by examining the different technologies used in the manufacturing of power devices, including Si, GaN, and SiC, considering their respective particularities and advantages. We will then analyze various approaches to the SPICE modeling of power devices, including compact models and macromodels. A significant portion of our presentation will be dedicated to the topic… Power Devices SPICE Modeling for Si, GaN and SiC Technologies
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Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment uncovers SI/PI issues early in the design process, leading to faster signoff of designs. With analysis shifting left in the design cycle, design teams can achieve efficient signoff of… Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis |
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This webinar will cover how the Ansys simulation tools are now widely used in many low-frequency (LF) EM applications, such as wireless charging, power supplies, transformers, magnetic latches and actuators, PCB/ECAD, and more. Discover how Ansys Maxwell enables rapid and accurate simulation of EM fields in electronic and consumer devices to reduce design iterations, component… Power Innovations in Consumer Electronics Using LF EM Solutions
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Join us to learn more about the AI and Simulation Revolution in this upcoming webinar. We're revolutionizing engineering simulation with the power of Artificial Intelligence with SimAI, AnsysGPT, and Ansys AI+. Overview At Ansys, we are revolutionizing engineering simulation with the power of Artificial Intelligence. Our AI-augmented simulation technology is a game-changer, bringing unprecedented speed,… Introducing Ansys AI: A New Chapter in Engineering Simulation |
1 event,
FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers, project managers, technical managers, researchers, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience, – the universities will present new and exciting projects, and the vendors… FPGA Forum 2024 – Norway |
3 events,
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This “Getting Started” webinar focuses on the first, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing, self-checking tests, messaging, reports, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. The “transaction” in transaction-based testing is just a fancy word for an… Essential Steps to Simplify VHDL Testbenches Using OSVVM
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Leadership in the RISC-V Era: India's Exciting New Opportunity Join SiFive for an informative afternoon session, featuring key thought leaders in the fast -growing global RISC-V ecosystem. Krste Asanovic, inventor of RISC-V and SiFive founder will be joined by academic and business leaders to provide an overview of RISC-V and the latest advances as well as… SiFive RISC-V Day |
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The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts. |
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The demand for Custom ICs is on the rise globally along with high proliferation of semiconductor content. Higher requirements on power, performance, area, and yield, as well as other factors such as advanced process nodes and mission-critical applications have increased the need for accurate verification across process, voltage, and temperature corners, as well as local… SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies
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This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Venue – Cadence Design System, Bengaluru & Online Time Session 15:00 GMT Welcome and introduction - Mike Bartley, Tessolve 15:00 GMT Cadence 16:00 GMT Tessolve 16:30 GMT TBD 17:00 GMT Close About DVClub The principal… DVClub India – Using AI/ML in Design Verification |
3 events,
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Join us virtually to hear Pat Gelsinger and Stu Pann discuss progress in delivering the world's first Systems Foundry for the AI Era to meet the ever-expanding demands of the Siliconomy. The keynote will feature special appearances by U.S. Secretary of Commerce Gina M. Raimondo and Microsoft Chairman and CEO Satya Nadella. Be sure to stick… Intel Foundry Services (IFS) Direct Connect
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Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1, 2.0 and 3.0, Siemens Avery CXL Verification IP. Compute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as… Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity |
2 events,
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The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations, education/mentoring, or business or industry leadership. The award was established as a tribute to Phil Kaufman, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. DR. LAWRENCE… Phil Kaufman Award & Banquet |
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Attend and hear research, challenges, and breakthroughs as you gather with colleagues in San Jose Join other leading researchers who are solving challenges in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications. Five days of exciting content and connecting with your community Plenary talks Technical presentations Networking… SPIE Advanced Lithography + Patterning |
3 events,
Where technology, community and commerce converge MWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator, device manufacturer, technology provider, vendor, content owner, or are simply interested in the future of tech, you need to be here. Why? Because it’s the one time of year where… MWC 2024
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Please join us for our in-person Synopsys Technical Forum, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing's mask synthesis, mask data prep, and lithography simulation solutions. The Tech Forum is peer-to-peer, giving you the opportunity to hear how your lithography colleagues have… Synopsys Technical Forum 2024 |
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Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting, unveiling the power of Capital™ Service Explorer. Discover innovative strategies to diagnose issues swiftly, minimizing downtime and optimizing product performance. Explore real-world examples showcasing how Capital Service Explorer facilitates the identification of commonalities among multiple… From code to solution: tools and tactics for aerospace fault code troubleshooting |
3 events,
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Shift Left with the Modern Design Center Artificial intelligence (AI) is redefining high-speed digital designs. Your ability to design, simulate, and test — using an automated, integrated workflow — is what will set you apart. Whether you are a design team leader, digital designer, or system engineer, this one-day event is for you. We have… Keysight EDA Connect World Tour: Santa Clara – High Speed Digital |
4 events,
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Shift Left with the Modern Design Center Artificial intelligence (AI) is redefining communication and connectivity. Your ability to design, simulate, and test — using an automated, integrated workflow — is what will set you apart. Whether you are a design team leader, RF designer, or system engineer, this one-day event is for you. We have… Keysight EDA Connect World Tour: Santa Clara – RF Day
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We often think of Design for Manufacturing (DFM) as the sole responsibility of the fabricator. Over the years, many OEMs have implemented DFM as a final check in their release process, but that approach does not prevent issues within a design from piling up and being left for a DFM engineer to identify and communicate… Manufacturing driven design – DFM within an Xpedition Flow |
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