Siemens EDA
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Improving Initial RTL Quality
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without waiting for a testbench. This webinar will introduce you to a testbench-free designer-driven verification flow, resulting in a lower cost… Improving Initial RTL Quality
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A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X
If you can’t make the live session, please register anyway and you’ll get the link to the recorded session afterward. The complicated silicon defect types and defect distribution for advanced technologies can lead to initially very low yield for new design with new technology. To ramp up yield as quickly as possible to meet the market window,… A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X
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Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But what about verifying out-of-order cases? Or intermittently dropped bytes? Granted, a testbench can be written to look out for these issues, but as the layers… Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
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DVCon Europe 2021
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques,… DVCon Europe 2021
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Osmosis 2021 (OneSpin User Group)
What is Osmosis? Osmosis is the name for all users’ group events for customers and partners of OneSpin: A Siemens Business, provider of electronic design automation (EDA) tools for integrated circuit (IC) integrity verification. Though the Osmosis name is an acronym (OneSpin Meeting on Solutions, Innovation, & Strategy), it was chosen intentionally because of what the term osmosis represents: movement in two directions. In this… Osmosis 2021 (OneSpin User Group)
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Understanding Random Stability in SystemVerilog and UVM
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability. In this webinar, we explain: Random stability in SystemVerilog… Understanding Random Stability in SystemVerilog and UVM
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28th Electronic Design Process Symposium
In 2021, the Electronic Design Process Symposium (EDPS) is in its 28th year, and it continues to serve as a leading forum for thought leaders of the design community from industry participants as well as academia. We invite industry leaders to discuss state-of-the-art improvements to the electronic design processes and CAD methodologies, emphasizing trends and… 28th Electronic Design Process Symposium
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Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
Presented by Todd Westerhoff, Product Marketing Manager for High-Speed System Design, Siemens EDA Abstract The PCB layout team has just handed you back a routed database with hundreds of serial links routed to your specifications — now what? How can you validate every link-as-routed for protocol compliance before releasing the design? If you're like most… Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
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DVCON India
This conference will give you ample opportunities to share and highlight your technical contibutions in the areas of Verificaiton and Validations, Methodology & Automation, Functional Safety & Security, Low Power and Mixed Signal Design, Static and Formal methods and Digital Twins and SystemC Modeling. Kindly use this opportunity and register yourself for the conference.… DVCON India
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Introduction to Questa Lint and CDC for Designers
Have you ever had RTL code that passes simulation but still fails due to things like unreachable code, out-of-range violations, or incorrect order of execution? Have you ever dealt with a multi-clock design that had glitch or reconvergence issues in silicon that took weeks to root cause? See how the correct verification tools can resolve… Introduction to Questa Lint and CDC for Designers
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SemIsrael Tech Webinar
SemIsrael Expo is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design… SemIsrael Tech Webinar
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DATE 2022
Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test DATE conference is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a… DATE 2022