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3D IC

Ansys, March 23, 2023

Thermal Integrity Challenges and Solutions of Silicon Interposer Design

In this latest installment of the year-long 3D-IC webinar series, Dr. Lang Lin will discuss the Thermal Integrity issues associated with 3D-IC designs. The presentation… Read More »Thermal Integrity Challenges and Solutions of Silicon Interposer Design

Ansys, January 24, 2023

Signal Integrity Issues for Silicon Interposers

The development of applications like high-performance computing, Artificial Intelligence (AI) processors, and Central Processing Unit (CPU) and Graphical Processing Unit (GPU) chips involves advanced packaging… Read More »Signal Integrity Issues for Silicon Interposers

Cadence, Multi-Chiplet

CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges

Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat,… Read More »CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges

Cadence, Multi-Chiplet

CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these… Read More »CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

Cadence, Multi-Chiplet

CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package,… Read More »CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

Cadence, Multi-Chiplet

CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA,… Read More »CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform