In this latest installment of the year-long 3D-IC webinar series, Dr. Lang Lin will discuss the Thermal Integrity issues associated with 3D-IC designs. The presentation will cover thermal hotspots, mechanical stresses induced by thermal issues,…
The development of applications like high-performance computing, Artificial Intelligence (AI) processors, and Central Processing Unit (CPU) and Graphical Processing Unit (GPU) chips involves advanced packaging technologies that radically alter traditional design methodologies and flows. Designers…
Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address…
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal…
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do…
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during…
IEEE International 3D System Integration Conference (3DIC) November 15-18, 2021 Raleigh, North Carolina, USA After a one-year hiatus, 3DIC will once again unite 2.5D/3D researchers and developers from all around the world. This year’s conference…