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Aldec, May 5, 2022

FPGA Verification Architecture Optimization with UVVM

Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification… FPGA Verification Architecture Optimization with UVVM

Aldec, April 14, 2022

Running CDC Analysis with Xilinx Parameterized Macros

Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other,… Running CDC Analysis with Xilinx Parameterized Macros

Aldec, April 28, 2022

Webinar: FPGA Design Architecture Optimization

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the… Webinar: FPGA Design Architecture Optimization

Aldec, March 10, 2022

Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification techniques such as constrained random… Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Aldec, February 24, 2022

Automating UVM flow using Riviera-PRO’s UVM Generator

UVM is a versatile verification methodology that enables users to run advanced verification flows for large scale FPGAs and SoC FPGAs. However, because of its advanced nature, writing UVM from scratch can be a complex… Automating UVM flow using Riviera-PRO’s UVM Generator

Aldec, January 20, 2022

Increase your productivity with Continuous Integration flows

Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly,… Increase your productivity with Continuous Integration flows

Aldec, February 10, 2022

Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)

PCIe-based FPGA designs are becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with… Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)

Aldec, December 2, 2021

LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)

Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect – such as AXI, APB, AHB, Avalon or Wishbone – for both internal (IP-level) and external communication. A recently added feature to Aldec’s… LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)

Aldec November 4

Constraint Random Verification with Python and Cocotb

Abstract: Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean writing test code can’t be enjoyable and productive! Cocotb, an approach to use… Constraint Random Verification with Python and Cocotb