Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address… CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal… CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do… CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during… CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform