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Cadence Integrity

Cadence, Multi-Chiplet

CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges

  • April 6, 2022February 2, 2022

Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat,… Read More »CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges

Cadence, Multi-Chiplet

CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

  • March 23, 2022February 2, 2022

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these… Read More »CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

Cadence, Multi-Chiplet

CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

  • March 9, 2022February 2, 2022

System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package,… Read More »CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

Cadence, Multi-Chiplet

CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform

  • February 23, 2022February 2, 2022

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA,… Read More »CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform

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