Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT Close About DVClub The principal goal of each DVCLUB meeting is… Auto-generation of Verification Infrastructure for IP to SoC
High-fidelity simulations in the ever-widening realm of complete systems analysis requires incorporating vendor-supplied models for accuracy. However, vendors are reluctant to share their proprietary intellectual property. Cadence enables the ecosystem and supports model creators by allowing… Enabling Electromagnetic Simulations with Encrypted Components
Event Overview Date: Monday, November 13, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing… CadenceCONNECT: The Race Is On!
STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment.… STAC Summit
Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite… Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave, such as non-linear addressing,… Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
We’re inviting global partners and customers to our upcoming Samsung Foundry Forum (SFF) and Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023. The events will provide opportunities to share insights and innovative technologies to build a… Samsung Foundry Forum 2023 EMEA
EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring… EPEPS 2023
The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities… Enhance Verification Quality with the Xcelium Mixed-Signal App
Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis