On-chip monitors and debug structures can dramatically simplify debug, validation, analytics, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG. In this… Boost SoC debug and analytics with embedded software and smart monitors
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31 to Sunday, April 2, 2023 in Santa Barbara, California, USA.… Latch-Up 2023
The complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area),… Power Intent Management for Large SoCs
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it… Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case… Accelerating Complex SoCs Prototyping with Protium X2
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect – such as AXI, APB, AHB, Avalon or Wishbone – for both internal (IP-level) and external communication. A recently added feature to Aldec’s… LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to… Avoiding SoC Security Threats – What Verification Engineers Should Know
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the… UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in the SOC Design process is… Agile Planning for SoC Design