Latch-Up 2023
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31… Read More »Latch-Up 2023
SoC
Power Intent Management for Large SoCs
The complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as… Read More »Power Intent Management for Large SoCs
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI… Read More »Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
Accelerating Complex SoCs Prototyping with Protium X2
This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges… Read More »Accelerating Complex SoCs Prototyping with Protium X2
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect – such as AXI, APB, AHB, Avalon or Wishbone – for both internal… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Avoiding SoC Security Threats – What Verification Engineers Should Know
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic… Read More »Avoiding SoC Security Threats – What Verification Engineers Should Know
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Agile Planning for SoC Design
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design.… Read More »Agile Planning for SoC Design