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Siemens, November 16, 2023

Boost SoC debug and analytics with embedded software and smart monitors

On-chip monitors and debug structures can dramatically simplify debug, validation, analytics, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG.  In this… Boost SoC debug and analytics with embedded software and smart monitors

Mirabilis, March 10, 2022

Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)

• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it… Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)

Cadence Protium, January 19, 2022

Accelerating Complex SoCs Prototyping with Protium X2

This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case… Accelerating Complex SoCs Prototyping with Protium X2

Aldec, December 2, 2021

LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)

Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect – such as AXI, APB, AHB, Avalon or Wishbone – for both internal (IP-level) and external communication. A recently added feature to Aldec’s… LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)

Avoiding SoC Security Threats – What Verification Engineers Should Know

Avoiding SoC Security Threats – What Verification Engineers Should Know

Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to… Avoiding SoC Security Threats – What Verification Engineers Should Know

Sep 23 Aldec

UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the… UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?