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Cadence Protium, January 19, 2022

Accelerating Complex SoCs Prototyping with Protium X2

  • January 19, 2022January 5, 2022

This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges… Read More »Accelerating Complex SoCs Prototyping with Protium X2

Aldec, December 2, 2021

LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)

  • December 2, 2021November 29, 2021

Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect – such as AXI, APB, AHB, Avalon or Wishbone – for both internal… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)

Avoiding SoC Security Threats – What Verification Engineers Should Know

Avoiding SoC Security Threats – What Verification Engineers Should Know

  • September 30, 2021September 23, 2021

Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic… Read More »Avoiding SoC Security Threats – What Verification Engineers Should Know

Sep 23 Aldec

UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

  • September 23, 2021September 20, 2021

Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

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