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Aldec, June 23, 2022

Advances in OSVVM’s Verification Data Structures

  • June 23, 2022June 20, 2022

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures

Aldec, June 16, 2022

OSVVM’s Test Reports and Simulator Independent Scripting

  • June 16, 2022June 14, 2022

According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging.  As a result, we need good scripting to simplify… Read More »OSVVM’s Test Reports and Simulator Independent Scripting

Aldec, May 26, 2022

Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

  • May 26, 2022May 12, 2022

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your… Read More »Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

VHDL, NOvember 19, 2021

Everything you wanted to know about VHDL configurations

  • November 19, 2021November 8, 2021

VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary. This webinar seeks to… Read More »Everything you wanted to know about VHDL configurations

Aldec October 21

Using OVL for Assertion-based Verification of Verilog and VHDL Designs

  • October 21, 2021October 6, 2021

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs

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