OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify… Read More »OSVVM’s Test Reports and Simulator Independent Scripting
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or… Read More »Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your… Read More »Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on… Read More »FPGA Verification Architecture Optimization with UVVM
VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary. This webinar seeks to… Read More »Everything you wanted to know about VHDL configurations
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs