VHDL

VHDL, NOvember 19, 2021

Everything you wanted to know about VHDL configurations

VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary. This webinar seeks to… Read More »Everything you wanted to know about VHDL configurations

Aldec October 21

Using OVL for Assertion-based Verification of Verilog and VHDL Designs

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs