IP
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Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
Join industry experts from aerospace, government, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI), highlighting some of the technological, manufacturing, and economic complexities as well as security, reliability, and safety challenges. The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research… Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
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Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software, this webinar will offer key insights into… Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
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Why Chiplets with UCIe are the Next Big Thing
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an open industry standard, to communicate with each other. Combined in a Systems-on-Package (SoP), they provide superior performance, reduced power consumption, and increased design flexibility for customized applications… Why Chiplets with UCIe are the Next Big Thing
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ASIP University Day 2023
ASIP University Day: Domain-Specific Processor Design using ASIP Designer Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not flexible enough. Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as… ASIP University Day 2023
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Silvaco UseRs Global Event (SURGE) 2023 – Korea
Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – Korea
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Boost SoC debug and analytics with embedded software and smart monitors
On-chip monitors and debug structures can dramatically simplify debug, validation, analytics, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG. In this webinar, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative… Boost SoC debug and analytics with embedded software and smart monitors
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Webinar Series | RISC-V Ready for Prime Time?
Join us for session II of our webinar series where we delve into the intricacies of RISC-V core integration and explore strategies to overcome the unique verification challenges that design and verification engineers encounter along the way. Whether you're an engineer looking to enhance your understanding of RISC-V or a technology enthusiast keen on staying… Webinar Series | RISC-V Ready for Prime Time?
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System Simulation of Versal ACAP Designs
AVersal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads, including machine learning, embedded computing, and high-performance computing. In this… System Simulation of Versal ACAP Designs
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Latest Innovations and Updates in ASICs
In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. Topics Include: - OpenFrame - a new version of Caravel that gives 50% more area - GPIO configuration questions - The new cocotb testing framework… Latest Innovations and Updates in ASICs
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Silvaco UseRs Global Event (SURGE) 2023 – EMEA
Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – EMEA
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Silvaco UseRs Global Event (SURGE) 2023 – Taiwan/Singapore
Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – Taiwan/Singapore
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FPGA Frontrunner Meet & Greet
Thales 350 Longwater Avenue, Reading, United KingdomThe FPGA Front Runners event will be hosted by Thales at their venue in Reading. The event will focus on “Security at System Level, and what security features we need in our FPGA to support this”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What is Security in FPGA-based… FPGA Frontrunner Meet & Greet