Webinar
Benefits of a Common Methodology for Emulation and Prototyping
Overview Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest in both platforms? Join our experts to understand why you should consider bridging emulation and… Read More »Benefits of a Common Methodology for Emulation and Prototyping
UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply do not scale up any longer. Even to map a large logic design to a modern-day FPGA takes many hours.… Read More »UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X
If you can’t make the live session, please register anyway and you’ll get the link to the recorded session afterward. The complicated silicon defect types and defect distribution for advanced technologies can lead to initially very low yield for new design with new technology. To ramp up yield as quickly as possible to meet the market window,… Read More »A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X
Learn About SiCure – Silvaco’s New IR Drop and Thermal Analysis Solution
Learn About SiCure – Silvaco’s New IR Drop and Thermal Analysis Solution Silvaco introduces SiCure, an exciting new development tool for IR-drop and thermal analysis. While being very accurate, SiCure is an extremely intuitive and easy to use tool requiring minimal data input. Now it is easier than ever to find layout issues that will… Read More »Learn About SiCure – Silvaco’s New IR Drop and Thermal Analysis Solution
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But what about verifying out-of-order cases? Or intermittently dropped bytes? Granted, a testbench can be written to look out for these issues, but as the layers… Read More »Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Agile Planning for SoC Design
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in the SOC Design process is a must. At the same time, the era of innovation is changing the way teams organize their work. Driven by… Read More »Agile Planning for SoC Design
Exploring Andes’ NX27V Vector Processor Instructions
Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), on September 29, 2021, at 09:00 AM PDT for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension. In this session, Dr. Tran presents examples using vector instructions based on Andes NX27V. He discusses NX27V performance,… Read More »Exploring Andes’ NX27V Vector Processor Instructions
Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
While IoT devices may seem simple to the end users (which is good), the electrical design complexity of these devices is often very high. Designers are required to work with limited board space while functionality and speed requirements continue to increase. These tight spaces, combined with the required highspeed signaling, leads to increased susceptibility to… Read More »Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
IP Based Digital Design Management that Goes Beyond the Basics
oin us on Thursday, September 30th to learn why common design management capabilities are not enough and what next generation capabilities are needed for IP based digital design management. Register Today! Here’s what you can learn: Complete digital design management checklist Tagging, branching, and merging Project BOM and IP conflicts Logistics: The webinar will be… Read More »IP Based Digital Design Management that Goes Beyond the Basics
Avoiding SoC Security Threats – What Verification Engineers Should Know
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious software. These challenging problems must be addressed pre-silicon and require rigorous… Read More »Avoiding SoC Security Threats – What Verification Engineers Should Know
Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
With advanced packaging and interface solutions, it is possible to connect multiple CPU clusters (near or far) and share external memory resources among them. We will review some of the IPs required to build such a platform and recommend applications that can benefit from it. This webinar will be useful to designers, architects, and application… Read More »Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems