Advanced Physical Design using OpenLANE/Sky130
Physical Design or PnR (Place and Route) is the core of any IC design cycle. From a RTL netlist to final tape-out, each phase of PnR brings it’s own challenges… Read More »Advanced Physical Design using OpenLANE/Sky130
2022 R2: What’s New in Ansys Signal & Power Integrity
About this Event The 2022 R2 Ansys Signal and Power Integrity release introduces significant simulation improvements for electronic printed circuit boards, IC packages, and interposers. Ansys SIwave delivers new features,… Read More »2022 R2: What’s New in Ansys Signal & Power Integrity
Has the Time for Analog Automation Finally Come?
The semiconductor industry is experiencing explosive growth, driven by emerging applications such as AI, 5G, IoT and automotive. To keep pace, design teams have deployed sophisticated CAD tools that can… Read More »Has the Time for Analog Automation Finally Come?
Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory Process
When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco… Read More »Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory Process
CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
Moderators: Ankur Srivastava (U. of Maryland) and Swarup Bhunia (U. of Florida) Panelists: - Mike Borza, Synopsys - Brian Night, Microsoft - Pompei Len Orlando, Air Force Research Lab (AFRL)… Read More »CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
Fast and Accurate Functional ECOs with Synopsys Formality ECO
To achieve maximal quality of results (QoR) in synthesis, it requires leveraging retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys Fusion Compiler™ implementation solution. However,… Read More »Fast and Accurate Functional ECOs with Synopsys Formality ECO
Sustainability for Semiconductors
Don’t miss your chance to join this important conversation with industry leaders that are making an impact on the reduction of the semiconductor carbon footprint. Donna Yasay Senior Leader, Solutions… Read More »Sustainability for Semiconductors
FPGAs for AI and AI for FPGAs
Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism, while being flexible… Read More »FPGAs for AI and AI for FPGAs
Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow
Wireless communication is at the heart of the technological revolution of the past few decades and RF circuits are what enable wireless systems to communicate with each other. The design… Read More »Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow
A Key principle to successful tape-outs for Cadence Virtuoso users 10am PDT
As working remotely and virtually has become the new norm, collaboration and coordination between colleagues has its challenges and its obstacles. If you are using Cadence Virtuoso and working on… Read More »A Key principle to successful tape-outs for Cadence Virtuoso users 10am PDT
Centralized Register Design and Verification from a Golden Specification
Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents your… Read More »Centralized Register Design and Verification from a Golden Specification
Hot Chips 2022
HC34(2022) (advance program) will take place virtually from Sunday, August 21 - Tuesday, August 23, 2022. All HC33(2021) conference content open to public. Visit https://hc33.hotchips.org. Since it started in 1989, HOT… Read More »Hot Chips 2022