Addressing Silent Data Errors for Resilient Data Centers
Mark your calendar to join us on Thursday, May 18 at 11 a.m. EDT for an Open Compute Project (OCP) Foundation educational webinar on Addressing Silent Data Errors for Resilient Data Centers. During the webinar, you will learn: What is the magnitude of silent data errors (SDE) How does SDE impact end users What is… Read More »Addressing Silent Data Errors for Resilient Data Centers
Annual ESDA Membership Meeting & CEO Outlook
Keysight 5301 Stevens Creek Blvd, Building 5, Santa Clara, United StatesThe evening begins at the Keysight office, Thursday, May 18, at 5:00pm with the ESD Alliance Annual Membership Meeting. You'll get an overview of the past year's activities and discover what's in store for 2023. The meeting flows directly into a Welcome Reception followed by the powerful CEO Outlook. Enjoy a lively, nourishing networking reception that kicks off the CEO Outlook… Read More »Annual ESDA Membership Meeting & CEO Outlook
ISCAS 2023
Monterey, CA Monterey, CA, United StatesThe IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the active fields of theory, design and implementation of circuits and systems. Keynote Speakers Dr. Margaret Martonosi Margaret Martonosi is the US National Science Foundation’s (NSF)… Read More »ISCAS 2023
Embedded Vision Summit 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why attend? It's a First-Rate Program with Powerful Insights into Practical Perceptual AI. Join us for four days of learning—from tutorials to deep-dive days, covering the latest technical insights,… Read More »Embedded Vision Summit 2023
Extending RISC Processors into Flexible Accelerators using ASIP Designer
Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function… Read More »Extending RISC Processors into Flexible Accelerators using ASIP Designer
DENSO discusses Verification of network relay performance using VisualSim
Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. Efficient in-vehicle network development through simulation combining network and ECU hardware and software elements Time Zone: Japan - 3:00 PM (In Japanese) Asia - 3:00… Read More »DENSO discusses Verification of network relay performance using VisualSim
Advancing MRAM Technology with Atomistic Spin Dynamics Simulations
In this event, experts from Martin-Luther-Universitat Halle Wittenberg, University of York, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. Investigating the potential of novel magnetic tunnel junction (MTJ) materials… Read More »Advancing MRAM Technology with Atomistic Spin Dynamics Simulations
Requirements for Multi-Die System Success
Wednesday, May 24, 2023 and Thursday, May 25, 2023 The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning, die/package co-design, secure… Read More »Requirements for Multi-Die System Success
Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
Synopsys Webinar | Wednesday, May 24, 2023 | 10:00 - 10:45 a.m. IST Engineering resources are getting stretched thinner and thinner as design complexity increases. Automation is a significant driver to help engineers overcome resource constraints and meet critical time-to-market windows. Two of the top three challenges cited by the engineering community in a recent… Read More »Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
Don’t Take the Risk, Formally Verify Your RISC-V Cores
Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. In this… Read More »Don’t Take the Risk, Formally Verify Your RISC-V Cores
SiFive Maximizes Compute Density With Its RISC-V Processor Cores
IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density - compute horsepower per mm2 and per mW (e.g SPECint2006/mm2) - has been a driving goal for SiFive’s portfolio of… Read More »SiFive Maximizes Compute Density With Its RISC-V Processor Cores
STAC Summit
New York Marriott Marquis 1535 Broadway, New York City, NY, United StatesSTAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment.