Improving Efficiency and Quality of Verification Environments with Automation
Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. Verification environments are often more complex than the designs they help verify.… Read More »Improving Efficiency and Quality of Verification Environments with Automation
RISC-V Con
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesIn order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions. Seventeen years in business and a Founding Premier member… Read More »RISC-V Con
Synopsys Photonic Symposium
Photonics and photonic IC technologies are crucial to support rapidly evolving internet, healthcare, mobility, and security needs. Driven by data communications, photonic ICs are moving rapidly from the laboratory to mainstream and fueling a wave of innovations and product introductions. Join our virtual Photonic Symposium to hear about the latest developments, application requirements, best practices,… Read More »Synopsys Photonic Symposium
Jasper User Group 2022
Cadence San Jose, CA, United StatesReady to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual Jasper™ User Group Conference held on October 19 and 20 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the… Read More »Jasper User Group 2022
Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core performance of the simulator. We keep developing new performance optimizations that are delivered with each new release of Xcelium. It is easy to achieve… Read More »Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
Optimizing Simulations for Efficient Coverage Collection
Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation, collection and analysis of coverage on your designs might look challenging but with a few steps you can optimize your design flow to… Read More »Optimizing Simulations for Efficient Coverage Collection
The Dawn of AI Revolution in Chip Design
Abstract: We are at the dawn of an AI revolution for every human activity including chip design. The AI revolution in chip design is absolutely necessary because of key macro trends influencing chip design and would further accelerate the AI revolution in all other fields. In this talk I will start with my personal journey… Read More »The Dawn of AI Revolution in Chip Design
The Applied Superconductivity Conference
Hawaii Convention Center 1801 Kalākaua Ave, Honolulu, HI, United StatesThe Applied Superconductivity Conference is the premier international conference on applied superconductivity and quantum computing. Engineers, scientists and industry representatives interested in developments related to the electronics and materials for superconductors that are involved in any type of quantum system should attend. ASC'22 Conference Chair's Statement Aloha to ASC 2022 in Hawaii! On behalf of… Read More »The Applied Superconductivity Conference
Arm DevSummit
Palace of Fine Arts 3601 Lyon Street, San Francisco, CA, United StatesAfter two years of virtual networking, we’re thrilled to announce the return of Arm DevSummit in-person in October. As you’re a past attendee, we’re delighted to welcome you to this milestone event. Arm DevSummit is for people developing and deploying on Arm-based hardware. We want to give you, the future builders, the insight and edge… Read More »Arm DevSummit
TSMC 2022 OIP – California
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin the TSMC 2022 Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges! Register Now Learn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies Latest 3DIC chip stacking and advanced packaging… Read More »TSMC 2022 OIP – California
Protium Enterprise Prototyping: Higher Productivity, Lower Costs
Prototyping has become essential for chip and IP developers as they deal with exponentially greater testing requirements that come with growing design size, software content, and input data and workloads to run. The increasing complexity in prototyping has naturally increased costs, both in hardware, tools, and engineering talent. For many projects, build-your-own prototypes are no… Read More »Protium Enterprise Prototyping: Higher Productivity, Lower Costs
Synopsys Technology Symposium 2022 – UK
Hilton Reading Drake Way, Reading, United KingdomSynopsys Northern Europe is hosting a Technical Symposium providing updates on all aspects of doing state of the art designs at emerging and established nodes. This event provides an opportunity for users to stay connected with the latest products and innovations as well as getting tips & tricks and best practices that our experts will… Read More »Synopsys Technology Symposium 2022 – UK