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Design Methodology for Building Power Efficient RTL
The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically translate to efficiency gains in terms of energy anymore. That’s why regardless of the application area - networking, computation, or… Design Methodology for Building Power Efficient RTL
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Methodics User Group (MUG) – April 12, 2022
If your company uses 3rd party IP in their design process, it is important to consider how you will manage them to extract maximum leverage. Having a central library and consistent processes for managing both internal and 3rd party IP is vital step to get the most your investment. Learn how you can optimize 3rd… Methodics User Group (MUG) – April 12, 2022
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Synopsys Parasitic Extraction – Interconnect 2022
Why Attend? Join us at the upcoming SPEX-I 2022 Workshops to learn about the latest features and flows to address signoff parasitic extraction challenges for advanced digital SoC designs or complex custom designs using Synopsys’ StarRC™ solution. In this workshop, we will discuss key methods to improve design convergence, demonstrate newer technologies to improve TAT,… Synopsys Parasitic Extraction – Interconnect 2022
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In-Design EM Analysis for Microwave/RF Design and Verification Workflows
Overview 3D finite element method (FEM) and 3D planar method of moments (MoM) have become a standard design practice for ensuring the accuracy of the overall network simulation. However, without proper setup and use of electromagnetic (EM) analysis tools to define the structure and RF excitation (ports), designers can experience erroneous simulation results and/or excessively… In-Design EM Analysis for Microwave/RF Design and Verification Workflows
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Running CDC Analysis with Xilinx Parameterized Macros
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably. Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and BRAM… Running CDC Analysis with Xilinx Parameterized Macros
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CHIPS Alliance Spring Event
The CHIPS Alliance holds workshops in various locations throughout the year, based upon the needs of our project and members. Members of the CHIPS Alliance receive a number of complementary passes each year, based upon their membership level. Date: April 19, 2022 at 8 a.m. PT Schedule: Welcome / Opening Remarks: Rob Mains, CHIPS Alliance Chisel/FIRRTL… CHIPS Alliance Spring Event
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Linley Spring Processor Conference 2022
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesTechInsights is pleased to continue the semi-annual Linley Processor Conferences, established more than a decade ago. This year, the Linley Spring Processor Conference will return to Santa Clara on April 20-21, 2022 with a new hybrid format; if you can’t attend in person, you can tune in to our virtual livestream. Presentations will address processors… Linley Spring Processor Conference 2022
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Rapidly Scale and Reduce Time-to-Market for Your Designs with Synopsys Cloud
Presented by Sridhar Panchapakesan, Director, Program Management, Synopsys; Giancarlo DiPasquale, Sr Technical Specialist, Microsoft Talk Cloud has democratized access to increasing compute power by lowering barriers to entry, creating the flexibility to scale elastically, and enabling distributed workloads. But there is more to moving EDA to the cloud than simply swapping on-prem hardware for cloud;… Rapidly Scale and Reduce Time-to-Market for Your Designs with Synopsys Cloud
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What’s Behind the Infrastructure of the CORE-V Family
Automated code validation, continuous integration and test regression are cornerstones of OpenHW Group's community-based engineering process to develop and verify high-quality processor cores. OpenHW Group is deploying a state-of-the-art Test Automation and Continuous Integration environment to achieve these objectives across our diverse projects, resulting in faster development cycles with increased quality. In this webinar, Florian… What’s Behind the Infrastructure of the CORE-V Family
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2022 IEEE Custom Integrated Circuits Conference (CICC)
Renaissace Newport Beach 4500 MacArthur Blvd, Newport Beach, CA, United StatesThe IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design… 2022 IEEE Custom Integrated Circuits Conference (CICC)
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40th IEEE VLSI Test Symposium 2022
The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in the test, validation, yield, reliability, and security of microelectronic circuits and systems. Due to the COVID-19 worldwide situation, the 2022 edition of VTS will be a fully virtual interactive live event. Update: We offer an option for attendees to attend the first… 40th IEEE VLSI Test Symposium 2022
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D&R IP SoC Silicon Valley 2022
Computer History Museum 1401 N. Shoreline Blvd, Mountain View, CA, United StatesWhen : April 26th 2022 Where : Computer History Museum 1401 N. Shoreline Blvd Mountain View, CA 94043, USA D&R IP-SoC Silicon Valley 2022 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight… D&R IP SoC Silicon Valley 2022
12 events found.