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The FPGA Front Runners event will be hosted by Thales at their venue in Reading. The event will focus on “Security at System Level, and what security features we need in our FPGA to support this”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What is Security in FPGA-based… FPGA Frontrunner Meet & Greet |
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Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – Japan
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System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test (DFT) logic required for manufacturing tests has also become more complex. Increasing transistor density, combined with a growing mix of… Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
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Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT Close About DVClub The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe… Auto-generation of Verification Infrastructure for IP to SoC |
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Synopsys Webinar – Part II In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part II |
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ANSYS’ VIRTUAL USER CONFERENCE FOR ELECTRONICS, SEMICONDUCTORS AND PHOTONICS DESIGNERS Join us for the IDEAS Digital Forum — a place to catch up on industry best practices and the latest semiconductor, electronic, and photonic design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights by expert chip designers from… Innovative Designs Enabled by Ansys Solutions – IDEAS 2023
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Wall-modeled large eddy simulations (WMLES) of complex vehicle geometries offer highly accurate results but can be challenging in terms of speed and cost. In this webinar, learn how to maximize the throughput of these simulations with Fidelity CharLES and how the solver’s GPU acceleration lowers the cost of using WMLES in engineering design. We will… Large Eddy CFD Simulation for Automotive Aerodynamics
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In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. Topics Include: OpenFrame - a new version of Caravel that gives 50% more area GPIO configuration questions The new cocotb testing framework IPM - The… Latest Innovations and Updates in ASICs with Efabless |
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The IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS) will be held in Istanbul, Turkey 4-7 December 2023. As the flagship conference of IEEE Circuits and Systems Society in Region 8 (Europe, Middle East, and Africa), ICECS 2023 will consist of tutorials, plenary lectures, regular, special and poster sessions focusing on recent trends,… IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS) 
A worldwide connected Event !! IP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and… IP-SoC Conference 23 – Grenoble |
4 events,
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It’s time for our inaugural CadenceCONNECT: Conformal® User Group Conference and Technology Day held on December 5th at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers to share the latest design and verification practices based on Cadence’s Conformal family of solutions including logical equivalence checking (LEC), low power… Conformal User Group Conference 2023 and Technology Day
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Today's electronic products increasingly use Rigid-Flex PCBs to compress form factors, reduce weight, and increase cost-effectiveness. For many commercially available 3D numerical solver technologies (FEM and FDTD), the electromagnetic (EM) analysis of rigid-flex PCBs has always been challenging due to the complexity of the 3D designs. Much of this complexity comes from bending the board into… Rigid Flex PCB In-Design Electromagnetic Analysis Workflow |
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Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging Moore’s law, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome… Multi-Die System Verification with Siemens Avery UCIe VIP
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Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include: - Speed and power requirements lead to designs with multiple asynchronous clock domains on different I/O interfaces and data being transferred from one… Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques |
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Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – China |
1 event,
IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for… 69th International Electron Devices Meeting – IEDM |
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This webinar will demonstrate how Ansys tools can improve PCB designs for higher performance and reliability. Ansys Maxwell simulates low-frequency (LF) EM fields to identify potential EMI/EMC issues for shielding and grounding purposes. Engineers can also predict electric currents distributed throughout the PCB power traces and study the EM forces generated by the magnetic field… Solve EM Fields and Forces in PCBs for Consumer Electronics |
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The XXII International Workshop on the Physics of Semiconductor Devices (IWPSD 2023) is being jointly organized by the Indian Institute of Technology Madras in collaboration with Society for Semiconductor Devices and Semiconductor Society (India). This series of biennial workshops, started in 1981, provides a global forum for interaction between scientists and technologists working in the… International Workshop on Physics of Semiconductor Devices – IWPSD 2023
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Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator, Modus DFT Software Solution,… RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
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Are you seeking to achieve dramatic gains in product time to market? This webinar will explore the combined solution of proteanTecs deep data analytics solutions and the PDF Solutions Exensio platform for rapid NPI. This 30-minute program will include a presentation and a LIVE DEMO of the integration of PDF Solutions' Exensio platform and proteanTecs' deep data analytics… Accelerating New Product Introduction with Integrated End-to-End Analytics
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Synopsys Webinar – Part III In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part III |
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With increasing chip design complexity, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases, UPF creation and assembly are among the key capabilities to ease the implementation for complex… Automated Power Intent Management Pre-synthesis for Large SoC Designs |
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Webinar Overview: This webinar explores debugging SystemC code with basic tools, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without getting lost and obtaining information about SystemC simulation status. The session concludes with ideas on how to simplify debugging and… Debugging SystemC with GDB |
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The IEEE Rising Stars Conference is designed to inform, excite, enthuse, and bring together the top engineering Young Professionals and Students around the world to network and be inspired by each other. The program includes Technical Innovation Talks, Professional Development, Workshops & Competitions, and Networking Opportunities with industry and peers. The conference gathers Technical Professionals who are experts in emerging technologies such as: Autonomous… IEEE Rising Stars 2024 |
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The 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata, India, during January 6-10, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders, Indian and international industry bodies, and academic researchers in a… VLSID 2024 |