Cadence
Signal and Power Integrity Analysis with Sigrity Aurora
Join Cadence Training and Principal Application Engineer Vladimir Papic for this free technical Training Webinar. Cadence® Sigrity™ Aurora is a signal and power integrity (SI/PI) analysis solution, tightly integrated into the Allegro® PCB design environment. Bridging the gap between design and analysis with In-Design Analysis (IDA) features, Sigrity Aurora reads and writes directly to the… Signal and Power Integrity Analysis with Sigrity Aurora
Tackling Advanced Analog FinFET Front-End Design Challenges with Better Methodologies
Analog engineers adopting advanced FinFET technologies face many challenges that were not present when using planar transistors. Challenges in layout implementation have a direct impact on design specifications, and the luxury of over-margining is long gone. There are no third-order effects anymore, and managing layout effects, such as device and interconnect parasitics, variation, matching, and EM-IR,… Tackling Advanced Analog FinFET Front-End Design Challenges with Better Methodologies
ChipEx 2022
Expo Tel Aviv Tel Aviv, IsraelChipEx2022 The main event of the Israeli semiconductor industry, will be held on May 10, 2022 at the Expo Tel Aviv Conference Center. The event is expected to attract thousands of industry professionals including engineers, development managers, project managers, professional experts, procurement managers and more. ChipEx2022 will include lectures by the best experts from around the world who will deal… ChipEx 2022
AutoSense Detroit 2022
Michigan Science Center 5020 John R St, Detroit, MI, United StatesWe can’t wait to bring our community back together at the Michigan Science Center in Detroit. Join us 10-12 May to hear from over 50 speakers from companies across the autonomous vehicle perception supply chain, including AMD, BrainChip, Indie Semiconductor, ON Semiconductor, Siemens, STMicroelectronics, Cadence, Valeo, MOBIS, Synopsys, Veoneer, General Motors and Baraja. With a… AutoSense Detroit 2022
Arm and Cadence: Achieving Best Silicon Power, Performance, and Area
How do you deal with design requirements that span high performance, energy-efficient computing, and high-reliability implementation? To realize these goals, you need optimal design flows to deliver the best power, performance, and reliability. Join Cadence and Arm virtually for CadenceCONNECT: Arm and Cadence – Achieving Best Silicon Power, Performance, and Area. Learn about: High-performance design… Arm and Cadence: Achieving Best Silicon Power, Performance, and Area
Tackling Advanced Analog FinFET Back-End Design Challenges
The layout implementation of analog circuits in advanced FinFET technologies is becoming increasingly complex and challenging, with many new design rules to consider and multi-patterning, density rules, matching, and EM-IR concerns. These challenges can translate to longer layout turnaround times and reduced productivity. Join this CadenceTECHTALK to learn about silicon-proven technologies that improve layout engineering… Tackling Advanced Analog FinFET Back-End Design Challenges
Embedded Vision Summit
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe premier event for practical, deployable computer vision and visual AI, for product creators who want to bring visual intelligence to products. The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why attend? It's a First-Rate Program with… Embedded Vision Summit
Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0
The Peripheral Component Interconnect Express (PCIe®) high-speed interface has become the standard for computer expansion cards due to its high bandwidth combined with manageable component costs. However, the latest PCIe 6.0 release raises new challenges for design engineers, as the popular interface standard moves to pulse-amplitude modulation-4 (PAM-4) signaling for the first time. This webinar… Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0
European Test Symposium 2022
Casa Convalescencia Barcelona, SpainThe IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics and new trends in the area of electronic-based circuits and system testing, reliability, security and validation. ETS’22 will be held in Casa Convalescència, located in the historical modernist site Hospital de la Santa… European Test Symposium 2022
ITherm 2022
Sheraton Hotel & Marina 1380 Harbor Island Drive, San Diego, CA, United StatesWelcome to ITherm 2022 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems May 31 - June 3, 2022 Sheraton Hotel & Marina San Diego, CA USA (Co-Located with ECTC) Sponsored by the IEEE's Electronics Packaging Society (EPS), ITherm 2022 is an international conference for scientific and engineering exploration of thermal, thermomechanical and emerging… ITherm 2022
CadenceLIVE 2022 – Silicon Valley
Cadence San Jose, CA, United StatesAre you driving design change or feel you’ve overcome challenges that could impact the electronic revolution? CadenceLIVE™ offers you an opportunity to tell your story. Showcase your expertise and offer tips to address the complexities and challenges that engineers face today. CadenceLIVE Silicon Valley features peer presentations that highlight solutions, using Cadence® products, for today’s… CadenceLIVE 2022 – Silicon Valley
Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, disjointed design tools and flows provide a serious risk for product… Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows