Cadence
Introduction to the Joules RTL Power Solution
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar. Built on a multi-threaded frame-based architecture, the Cadence® Joules™ RTL Power Solution delivers 20X faster time-based RTL power… Introduction to the Joules RTL Power Solution
CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and… CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
DATE 2022
Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test DATE conference is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a… DATE 2022
Analog Fault Injection Simplifies ISO 26262 Compliance
As the automotive market moves toward electrified drivetrains and autonomous driving systems, chip makers increasingly need to design integrated mixed-signal chips that meet the ISO 26262 automotive certification. With these complex designs, designers will require automation to overcome the limits of using expert judgment to ensure compliance. Integrating functional safety analysis into their existing design… Analog Fault Injection Simplifies ISO 26262 Compliance
What’s New in Clarity 2022.1
The Cadence® Clarity™ 3D Solver, utilized by scores of customers across the globe, continues to accelerate design flows for leading companies in industries such as medical, hyperscale computing, 5G, automotive, and industrial internet of things (IIoT). The latest 2022.1 release continues to widen the gap between the Clarity 3D finite element (FEM) solver and alternatives in both… What’s New in Clarity 2022.1
GOMACTech 2022
Hyatt Regecy Miami 400 South East Second Avenue, Miami, FL, United StatesWELCOME TO GOMACTech 2022 Enabling Distributed Capabilities: Microelectronics Thriving in the Face of Change GOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce… GOMACTech 2022
CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis is extremely critical in 3D-ICs, since changing the die stack up later in the design process… CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address these concerns through simulation during system planning and continuing through signoff to accelerate the 3D-IC design cycle and avoid expensive… CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Formal Verification for non-specialists
Is formal verification ready for general use or do you need a PhD to use it? Larger companies continue to recruit formal PhDs into their verification teams while other less-qualified engineers seem reluctant to go beyond simplified formal "apps". So, what is the truth of the matter? Can non-specialist engineers become productive with formal? In… Formal Verification for non-specialists
In-Design EM Analysis for Microwave/RF Design and Verification Workflows
Overview 3D finite element method (FEM) and 3D planar method of moments (MoM) have become a standard design practice for ensuring the accuracy of the overall network simulation. However, without proper setup and use of electromagnetic (EM) analysis tools to define the structure and RF excitation (ports), designers can experience erroneous simulation results and/or excessively… In-Design EM Analysis for Microwave/RF Design and Verification Workflows
Linley Spring Processor Conference 2022
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesTechInsights is pleased to continue the semi-annual Linley Processor Conferences, established more than a decade ago. This year, the Linley Spring Processor Conference will return to Santa Clara on April 20-21, 2022 with a new hybrid format; if you can’t attend in person, you can tune in to our virtual livestream. Presentations will address processors… Linley Spring Processor Conference 2022
Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™
Learn how to formally verify your design by automatically generating SystemVerilog Assertions (SVA) for your block-level register specifications, chip-level RTL, and RTL connectivity at the SoC level using ARV-Formal™.