Cadence
DVClub Europe
Agenda (BST): Time Session Description Slides Videos 12.00 BST 16:30 IST Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve 12.05 BST 16:35 IST I’m Excited About Formal…My Journey From Skeptic To Believer Neil Johnson, Senior Product Engineering Manager, Siemens EDA… DVClub Europe
Cadence TECHTALK: Mixed-Signal SoC Verification Simplified with Xcelium Simulator (NA)
Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Join this webinar to learn how Cadence is providing effective verification and debug methodologies using RNM of analog blocks for mixed-signal SoC verification.
AI Hardware Summit
AI Hardware is evolving – and so are we! As machine learning models continue to grow in size and complexity, and more and more models enter production in enterprises worldwide, the way we approach accelerating these workloads is changing. At the front end, data-centricity is taking precedence over model-centricity. At the back end, AI practitioners… AI Hardware Summit
How to Improve Your Chip Design Performance and Productivity Using Machine Learning
New applications and technology are driving demand for even more compute power and functionality in the devices we use every day. This has resulted in the semiconductor industry experiencing strong growth based on technology like 5G, autonomous driving, hyperscale compute, industrial IoT, and many others. System-on-chip (SoC) designs are quickly migrating to new process nodes… How to Improve Your Chip Design Performance and Productivity Using Machine Learning
Benefits of a Common Methodology for Emulation and Prototyping
Overview Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest in both platforms? Join our experts to understand why you should consider bridging emulation and… Benefits of a Common Methodology for Emulation and Prototyping
Thermal Analysis for MMIC and RF PCB Power Applications
Overview The Cadence® Celsius™ Thermal Solver is now integrated with the Cadence AWR Design Environment® V16 platform, supporting electrothermal analysis for MMIC/RFIC, PCB, and module designs. Thermal analysis provides RF circuit designers with insight regarding operating temperatures that can degrade performance and threaten device reliability. This webinar will highlight how the Celsius Thermal Solver uses design… Thermal Analysis for MMIC and RF PCB Power Applications
Addressing Growing Security Challenges with JasperGold
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality. Recent microarchitectural vulnerabilities like “Meltdown” and “Row Hammer” that expose… Addressing Growing Security Challenges with JasperGold
Benefits of a Common Methodology for Emulation and Prototyping
Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest in both platforms? Join our experts to understand why you should consider bridging emulation and prototyping… Benefits of a Common Methodology for Emulation and Prototyping
Iternational Test Conferece
International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how… Iternational Test Conferece
CASPA 2021 Annual Conference
“GLOBAL SEMICONDUCTOR INNOVATION AND OUTLOOK” CASPA invites you to attend our 2021 Virtual Annual Conference on Saturday, October 16th, 2021 via Zoom. This Conference is a signature annual event for CASPA and has been well attended by the semiconductor professionals and executives from the Bay Area and worldwide. This year’s theme is Global Semiconductor Innovation… CASPA 2021 Annual Conference
CadenceLIVE Europe
For the last seventeen years, CadenceLIVE has brought together technology users, developers, and industry experts to connect, share ideas and best practices, and inspire design creativity. Attendees will have the opportunity to view exciting keynotes, attend interesting user presentations, and interact with Cadence® technology experts, peers, and our sponsors in our virtual Designer Expo. CadenceLIVE Europe 2021… CadenceLIVE Europe
Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
The Cadence® AWR® V16 for RF Design Excellence Webinar Series introduces the latest capabilities in Cadence® AWR Design Environment® Version 16 (V16), providing ready access to Cadence Clarity™ 3D Solver and Celsius™ Thermal Solver for unconstrained capacity to solve large-scale and complex RF systems directly from within the RF design platform. Our next webinar in… Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation