Cadence
Linley Fall Processor Conference 2021
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesFor more than a decade, The Linley Group has delivered the industry’s premier processor conferences. This year, the Linley Fall Processor Conference will return to Santa Clara on October 20-21, 2021. If you can’t attend in person, attend the virtual event on October 27-29 and November 3-5 with live Q&A and breakout sessions. Please stay… Linley Fall Processor Conference 2021
CadenceCONNECT – Mission Critical 2021
Overview CadenceCONNECT will introduce you to optimized design methodologies for mission-critical electronics system applications like A&D, safety, security, 5G, and others. The event brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification, and discovering new techniques for designing advanced silicon, SoCs, and systems. Keynote 10:00… CadenceCONNECT – Mission Critical 2021
DVCon Europe 2021
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques,… DVCon Europe 2021
Xcelium ML for 5X Faster Regression Throughput
Overview Regressions time often becomes one of the biggest challenges to meet the tight project schedule with increasing complexity of the SoC designs and shorter time to market. Verification engineers apply a coverage-driven methodology and run a large number of constrained random tests with multiple seeds in massive regressions to meet their coverage goals. Thus,… Xcelium ML for 5X Faster Regression Throughput
Intelligent Cross-Platform Workflows for RF PCB Integration
The last webinar in The Cadence® AWR® V16 for RF Design Excellence Webinar Seriesintroduces groundbreaking cross-platform workflows from AWR® software to Allegro® PCB Designer, which help to deliver up to a 50% reduction in turnaround time compared to competing solutions. RF IP integration within a larger mixed-signal PCB system is hampered by disjointed workflows between… Intelligent Cross-Platform Workflows for RF PCB Integration
28th Electronic Design Process Symposium
In 2021, the Electronic Design Process Symposium (EDPS) is in its 28th year, and it continues to serve as a leading forum for thought leaders of the design community from industry participants as well as academia. We invite industry leaders to discuss state-of-the-art improvements to the electronic design processes and CAD methodologies, emphasizing trends and… 28th Electronic Design Process Symposium
Boost LPDDR5 Verification from IP to System Level
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall… Boost LPDDR5 Verification from IP to System Level
Jasper User Group 2021
It’s time for our annual formal verification user group CadenceCONNECT: Jasper User Group 2021. This in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence® JasperGold® formal verification technologies and methodologies. This user group has become the premier industry event for formal experts… Jasper User Group 2021
CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
Join us as Cadence experts describe common challenges and solutions in creating an efficient and accelerated flow that will meet technical requirements for accurately measuring the power, energy, and system performance while making essential design tradeoffs to meet your aggressive time-to-market schedule. In this CadenceTECHTALK, you will learn how to: Address the challenges of accelerating… CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
How to Sign Off a 10 Billion+ Transistor Design in the Cloud
Advanced semiconductor applications such as artificial intelligence / machine learning (AI/ML) and graphic processing units (GPUs) fully leverage dense, advanced-node technology to push the extreme limits of design size. To signoff such large designs, engineers are increasingly relying on distributed compute methods to accelerate the signoff analysis. Furthermore, given lack of scalability of on-premises compute… How to Sign Off a 10 Billion+ Transistor Design in the Cloud
Fostering a Photonics Ecosystem for Sustainable Adoption
Integrated photonics adoption has made tremendous progress but is still slow and uneven outside of its most common use in data communications. What will it take for photonics to become a “standard” technology in the toolbox of system designers? Join Cadence for the sixth-annual CadenceCONNECT Photonics event on December 7 – 9 to find out… Fostering a Photonics Ecosystem for Sustainable Adoption
Bug Tracking with Indago Interactive for Specman
Join Cadence® Training and Principal Application Engineer Daniel Bayer for this free technical training webinar. The Indago™ Debug Platform is optimized for scalability, supporting debug of simulation runs as well as emulation, where support for loading large source files and handling huge amounts of probe data is a must. Join this free Cadence Training Webinar… Bug Tracking with Indago Interactive for Specman