Chiplet
IP Lifecycle Management for Chiplet-Based SoCs
Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges however, especially in the context of IP… IP Lifecycle Management for Chiplet-Based SoCs
Accelerating Mainstream Adoption of Multi-Die Systems
Synopsys recently hosted a panel discussion with Ansys, Bosch, Intel, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast of the panel where each company shares their view on the groundbreaking technology, what challenges lie ahead, and how companies can realize the promise of… Accelerating Mainstream Adoption of Multi-Die Systems
UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence,… UCIe-Based Chiplet Verification – from IP to SoC
Why Chiplets with UCIe are the Next Big Thing
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an open industry standard, to communicate with each other. Combined in a Systems-on-Package (SoP), they provide superior performance, reduced power consumption, and increased design flexibility for customized applications… Why Chiplets with UCIe are the Next Big Thing
Chiplet Summit
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions of the experts,… Chiplet Summit
Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the… Exploring the Advancement of Chiplet Technology and the Ecosystem
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level… Cracking the Power Code: Innovative Approach to SoC Power Optimization
Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level… Innovative Approach to SoC Power Optimization
Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC, GPU, mobile, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. For the past years, Synopsys and Ansys have… Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
Keysight EDA 2025 Launch event
New EDA Tools for 5G and AI Infrastructure Design We are ready to share the latest release of our electronic design automation (EDA) software suites. This update will help you design smarter with faster multidomain insights and workflows enhanced by artificial intelligence (AI). Get the Roadmap The webinar will kick off with an overview of… Keysight EDA 2025 Launch event
Chiplet Summit 2025
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesPosition Your Company as a Leader in an Emerging Technology. Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia). Share Thoughts with Key Experts and Analysts. Show Movers and Shakers How Your Products and Roadmap Will Drive the Industry. Meet Highly Motivated Customer Prospects. Only event totally dedicated to the skyrocketing chiplet… Chiplet Summit 2025