FPGA
FPGA Verification Architecture Optimization with UVVM
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make… Read More »FPGA Verification Architecture Optimization with UVVM
FPGA Design/Verification: Randomization
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design, and as a result their products have significantly more undetected bugs. Randomization can be used in many ways, but it… Read More »FPGA Design/Verification: Randomization
FPGA Design/Verification: Code, Functional and Specification Coverage
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you are in fact checking the right things in your testbench. Unfortunately, not many designers are applying… Read More »FPGA Design/Verification: Code, Functional and Specification Coverage
Versal ACAP Workshop Online
The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities. We’ll first cover the broader Versal ACAP device. We’ll then focus on a practical example, optimizing a given application for the… Read More »Versal ACAP Workshop Online
Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach. Creating a verification component (VC)… Read More »Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
OSVVM’s Test Reports and Simulator Independent Scripting
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay… Read More »OSVVM’s Test Reports and Simulator Independent Scripting
Advances in OSVVM’s Verification Data Structures
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage,… Read More »Advances in OSVVM’s Verification Data Structures
FPGA-Conference Europe
Hotel NH München Ost Conference Center Einsteinring 20, Munich, Aschheim, GermanyFPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is addressing that progress across all major manufacturers. It focusses on user-oriented, practically applicable solutions that developers can quickly integrate into… Read More »FPGA-Conference Europe
FPGAs for AI and AI for FPGAs
Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism, while being flexible and easily configurable, and also fast and power efficient. These unique properties make them appealing for DL acceleration in both data center and edge use… Read More »FPGAs for AI and AI for FPGAs
CDC Verification with Hard IP Blocks
Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are excluded from advanced linting. In fact, this is a correct approach as hard IP blocks are assumed to be functionally stable and may be excluded from both static and dynamic… Read More »CDC Verification with Hard IP Blocks
FPGA World 2022 – Stockholm
Afry Frösundaleden 2A, 169 70 Solna, Solna, SwedenThe FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based products, educational & industrial cases, and more. Registration for attendees is free and includes 2*coffee, lunch and go-home drink. Keynote speaker: Magnus Peterson, Synective Labs AB, Sweden Title: FPGAs for… Read More »FPGA World 2022 – Stockholm
FPGA World 2022 – Copenhagen
DTU Science Park 2800 Kongens, Lyngby, DenmarkThe FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based products, educational & industrial cases, and more. Registration for attendees is free and includes 2*coffee, lunch and go-home drink. Keynote speaker: Tero Rissa, Xilinx, Finland Title: Adaptable Domain-Specific Architecture (DSA) for… Read More »FPGA World 2022 – Copenhagen