Mirabilis
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level… Cracking the Power Code: Innovative Approach to SoC Power Optimization
Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level… Innovative Approach to SoC Power Optimization
DAC 2024
Moscone West San Francisco, CA, United StatesThe premier event for the design and design automation of electronic chips to systems. Autonomous Systems Electronics content in modern autonomous systems (e.g., automotive, robotics, drones, etc.) is growing at an increasingly rapid pace. Nearly every aspect of these complex systems uses smart electronics and embedded software to make our experiences safer, more energy-efficient and enjoyable. For… DAC 2024
IEEE SMC-IT/SCC 2024
Computer History Museum 1401 N. Shoreline Blvd, Mountain View, CA, United StatesThe International Conference on Space Mission Challenges for Information Technology (SMC-IT) and the Space Computing Conference (SCC) gather system designers, engineers, computer architects, scientists, practitioners, and space explorers with the objective of advancing information technology, and the computational capability and reliability of space missions. The forums will provide an excellent opportunity for fostering technical interchange… IEEE SMC-IT/SCC 2024
Chiplets: Building the Future of SoCs
Chiplets, also known as heterogeneous multi-die systems, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries, particularly fueled by the widespread adoption of AI technology. However, while the concept of using chiplets to construct larger chips to overcome… Chiplets: Building the Future of SoCs
IP-SoC Japan 24
Tokyo Convention Hall 3 Chome-1-1 Kyobashi, Toyo, JapanA worldwide connected Event !! D&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps… IP-SoC Japan 24
ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted
There are so many options for Network-on-Chip: ARM-Corelink CMN700, Arteris FlexNoC, open-source NoC interconnect, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet, do we… ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted
Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling
In a world where artificial intelligence and machine learning are embedded in critical applications—from real-time tracking and object detection to autonomous systems—the architecture behind these innovations must be both powerful and efficient. To help engineers and architects address these challenges, our upcoming webinar will demonstrate how System-Level Modeling can be a game-changer in optimizing the performance and… Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling
Chiplet Summit 2025
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesPosition Your Company as a Leader in an Emerging Technology. Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia). Share Thoughts with Key Experts and Analysts. Show Movers and Shakers How Your Products and Roadmap Will Drive the Industry. Meet Highly Motivated Customer Prospects. Only event totally dedicated to the skyrocketing chiplet… Chiplet Summit 2025
Simulating Auto Systems & E/E Architectures for power and performance using VisualSim
Estimating latency and power for different use-cases in Systems, ECU and Networks Overview: This session will focus on a common system-level simulation platform that can be shared by Semiconductor companies, Tier One Suppliers, OEMs in designing the entire E/E architecture. The transition to everything digital and electronics is causing a number of design challenges across the… Simulating Auto Systems & E/E Architectures for power and performance using VisualSim