Mirabilis
Automotive Ethernet Congress
Hilton Munich Airport Terminalstraße Mitte 20, 85356 München-Flughafen, Munich, GermanyThe ninth Automotive Ethernet Congress to be held on March 21 - 23, 2023 at the Hilton Munich Airport will look to address the following questions: Does the selected transmission technology support the transformation of the E/E architecture from hardware-based to software-centric? Does it offer the necessary flexibility and self-learning capability to be able to continuously… Read More »Automotive Ethernet Congress
Mapping SysML to hardware architecture
In this webinar, we will show how the SysML behavior models of a RADAR application can be mapped to a architecture model to measure the latency, throughput, power consumption, scheduling quality and response to bottleneck conditions. The application can be quickly mapped onto different architectures to meet the project requirements. This will enable better tuning… Read More »Mapping SysML to hardware architecture
Choosing the best modeling abstraction for your analysis
This webinar cover the modeling abstraction in the design of electronics, semiconductors and software. This webinar will definitely improve your modeling skills! --Is the abstraction right for your application and design goal? --How do you accelerate the simulation using abstraction? --Can you change the model of computation using abstraction to simplify the modeling effort? During… Read More »Choosing the best modeling abstraction for your analysis
DENSO discusses Verification of network relay performance using VisualSim
Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. Efficient in-vehicle network development through simulation combining network and ECU hardware and software elements Time Zone: Japan - 3:00 PM (In Japanese) Asia - 3:00… Read More »DENSO discusses Verification of network relay performance using VisualSim
DVCon India 2023
Radisson Blu Outer King Road, Bengaluru, IndiaOn behalf of the DVCon India 2023 steering committee, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference. We want to carry forward the momentum, excitement and the enthusiasm witnessed during last year’s edition into… Read More »DVCon India 2023
Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA. Key Takeaways: Discover the inner workings of FPGA components: Processor, Logic Elements, AIE/Tensor, and more. Understand latency… Read More »Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
Achieve 95% Accurate Power Measurement during Architectural Exploration
Are you in the conceptualization and architectural exploration phases, where assessing the power budget is of paramount importance? If you're looking to achieve precise power measurement for critical aspects like embedded software, power management algorithms, hardware configurations, and more, this webinar is tailor-made for you. Webinar: How to achieve 95%+ Accurate Power Measurement during… Read More »Achieve 95% Accurate Power Measurement during Architectural Exploration
VLSID 2024
ITC Royal Bengal Kolkata, IndiaThe 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata, India, during January 6-10, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders, Indian and international industry bodies, and academic researchers in a… Read More »VLSID 2024
Chiplet Summit
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions of the experts,… Read More »Chiplet Summit
GOMACTech 2024
Embassy Suites by Hilton Charleston Convention Center, Charleston, SC, United StatesGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC, and provides a forum for… Read More »GOMACTech 2024
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP