RTL
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From MATLAB to Optimized RTL in Minutes
As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from design implementation, often resulting in late discovery of performance issues. To mitigate this challenge, Cadence and MathWorks have collaborated to… From MATLAB to Optimized RTL in Minutes
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Low-Power Verification Using Xcelium Simulation
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on. The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. This webinar will focus… Low-Power Verification Using Xcelium Simulation
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ASIC Design Using OpenROAD
UCSC Silicon Valley Extension 3175 Bowers Ave, Santa Clara, CA, United StatesJoin us for a free, half-day workshop on the key concepts of an ASIC design physical implementation flow using OpenROAD. OpenROAD delivers a fast, barrier-free, and low-cost RTL-to-GDS, no-human-in-loop flow for design above 12nm and is one of the tools students can work with in UCSC Silicon Valley Extension VLSI Engineering program courses Knowing how to use open EDA tools boosts… ASIC Design Using OpenROAD
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Verisium Debug for UPF Low Power Design
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. What you… Verisium Debug for UPF Low Power Design
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Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc., correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past… Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
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A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO… A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
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Verisium Debug for UVM Testbench
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. What you will learn Understand… Verisium Debug for UVM Testbench
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RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator, Modus DFT Software Solution,… RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
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RapidGPT: Meet Your New AI-Powered Design Assistant
Join us for our upcoming webinar introducing RapidGPT, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session, explore how… RapidGPT: Meet Your New AI-Powered Design Assistant
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A Beginner’s Guide to RTL-to-GDSII Front-End Flow
In this Training Webinar, explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. Walk through the essential steps in creating integrated circuits, the building blocks of modern electronics. This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end… A Beginner’s Guide to RTL-to-GDSII Front-End Flow
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Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification
High-level design techniques and automation tools to address the limitations of traditional RTL, reduce verification times, improve performance, and manage growing design complexity—integrating seamlessly. What You'll Learn: This Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects.… Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification
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Fast Track RTL Debug with the Verisium Debug Python App Store
Working with debugging scripts locally and manually can be challenging, as can reusing and organizing them. What if there was a way to create your own app with the required functionality and to register it with the tool? The answer lies in the Verisium Debug Python App Store. Instantly add additional features and capabilities to… Fast Track RTL Debug with the Verisium Debug Python App Store