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Increase your productivity with Continuous Integration flows

Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to pinpoint which one introduced new bugs, and much time can… Read More »Increase your productivity with Continuous Integration flows

Introduction to the Joules RTL Power Solution

Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar. Built on a multi-threaded frame-based architecture, the Cadence® Joules™ RTL Power Solution delivers 20X faster time-based RTL power… Read More »Introduction to the Joules RTL Power Solution

Design Methodology for Building Power Efficient RTL

The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically translate to efficiency gains in terms of energy anymore. That’s why regardless of the application area - networking, computation, or… Read More »Design Methodology for Building Power Efficient RTL

Forum on Specification and Design Languages

LIT Open Innovation Center Altenberger Str. 69, Linz, Austria

FDL is a well-established international forum to exchange experiences and promote new trends in the application of languages, their associated design methods, and tools for the design of electronic systems. FDL stimulates scientific and controversial discussions within and in-between scientific topics as described below. The program structure includes research working sessions, embedded tutorials, panels, and… Read More »Forum on Specification and Design Languages

From MATLAB to Optimized RTL in Minutes

As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from design implementation, often resulting in late discovery of performance issues. To mitigate this challenge, Cadence and MathWorks have collaborated to… Read More »From MATLAB to Optimized RTL in Minutes

Low-Power Verification Using Xcelium Simulation

Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on. The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. This webinar will focus… Read More »Low-Power Verification Using Xcelium Simulation

ASIC Design Using OpenROAD

UCSC Silicon Valley Extension 3175 Bowers Ave, Santa Clara, CA, United States

Join us for a free, half-day workshop on the key concepts of an ASIC design physical implementation flow using OpenROAD.  OpenROAD delivers a fast, barrier-free, and low-cost RTL-to-GDS, no-human-in-loop flow for design above 12nm and is one of the tools students can work with in UCSC Silicon Valley Extension VLSI Engineering program courses Knowing how to use open EDA tools boosts… Read More »ASIC Design Using OpenROAD

Verisium Debug for UPF Low Power Design

Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. What you… Read More »Verisium Debug for UPF Low Power Design

Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise

As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc., correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past… Read More »Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise

A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues.   Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO… Read More »A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

Verisium Debug for UVM Testbench

Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. What you will learn Understand… Read More »Verisium Debug for UVM Testbench

RTL-to-GDSII Flow for ASIC Design Using Cadence Tools

Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator, Modus DFT Software Solution,… Read More »RTL-to-GDSII Flow for ASIC Design Using Cadence Tools