RTL
Pre-empt Late-stage Low Power Issues using Predictive Analysis
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout the design development cycle starting from architecture definition, RTL development, to final netlist tape-out. Conventionally, static low power flow constitutes defining and cleaning… Pre-empt Late-stage Low Power Issues using Predictive Analysis
Improving Initial RTL Quality
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without waiting for a testbench. This webinar will introduce you to a testbench-free designer-driven verification flow, resulting in a lower cost… Improving Initial RTL Quality
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom… UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
CHIPS Alliance Workshop
CHIPS Alliance, the open source RTL hardware and software development tool organization, is gathering to share milestones, progress, updates and more.
Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.… Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
FPGA Conference and Hackathon
We are changing the world through this. So you can! Join the FPGA Hackathon we organize in Kraków to learn more about the technology gaining more and more popularity! Sharing this passion is the reason why we decided to create this Conference and Hackathon. FPGA technology is one of the foundations for the revolutionary projects… FPGA Conference and Hackathon
Improving Design Power and Performance with RTL Architect
Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code. The first difficulty occurs during elaboration and synthesis. The RTL is converted to gates and the references to the source code are lost. The second difficulty is the gate-centric, implementation, PPA reports.… Improving Design Power and Performance with RTL Architect
Increase your productivity with Continuous Integration flows
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to pinpoint which one introduced new bugs, and much time can… Increase your productivity with Continuous Integration flows
Introduction to the Joules RTL Power Solution
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar. Built on a multi-threaded frame-based architecture, the Cadence® Joules™ RTL Power Solution delivers 20X faster time-based RTL power… Introduction to the Joules RTL Power Solution
Design Methodology for Building Power Efficient RTL
The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically translate to efficiency gains in terms of energy anymore. That’s why regardless of the application area - networking, computation, or… Design Methodology for Building Power Efficient RTL
Forum on Specification and Design Languages
LIT Open Innovation Center Altenberger Str. 69, Linz, AustriaFDL is a well-established international forum to exchange experiences and promote new trends in the application of languages, their associated design methods, and tools for the design of electronic systems. FDL stimulates scientific and controversial discussions within and in-between scientific topics as described below. The program structure includes research working sessions, embedded tutorials, panels, and… Forum on Specification and Design Languages