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Cadence, Multi-Chiplet

CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform

  • February 23, 2022February 2, 2022

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA,… Read More »CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform

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