Chiplet Summit 2025
Position Your Company as a Leader in an Emerging Technology. Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia). Share Thoughts with… Read More »Chiplet Summit 2025
Chiplet
Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and… Read More »Cracking the Power Code: Innovative Approach to SoC Power Optimization
Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and… Read More »Innovative Approach to SoC Power Optimization
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent… Read More »Exploring the Advancement of Chiplet Technology and the Ecosystem
Chiplet Summit
The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to… Read More »Chiplet Summit
Why Chiplets with UCIe are the Next Big Thing
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular… Read More »Why Chiplets with UCIe are the Next Big Thing
UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The… Read More »UCIe-Based Chiplet Verification – from IP to SoC
Accelerating Mainstream Adoption of Multi-Die Systems
Synopsys recently hosted a panel discussion with Ansys, Bosch, Intel, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite… Read More »Accelerating Mainstream Adoption of Multi-Die Systems
IP Lifecycle Management for Chiplet-Based SoCs
Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act… Read More »IP Lifecycle Management for Chiplet-Based SoCs