Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent… Read More »Exploring the Advancement of Chiplet Technology and the Ecosystem
The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to… Read More »Chiplet Summit
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular… Read More »Why Chiplets with UCIe are the Next Big Thing
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The… Read More »UCIe-Based Chiplet Verification – from IP to SoC
Synopsys recently hosted a panel discussion with Ansys, Bosch, Intel, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite… Read More »Accelerating Mainstream Adoption of Multi-Die Systems
Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act… Read More »IP Lifecycle Management for Chiplet-Based SoCs
SEMICON Japan is the premier event that brings together the semiconductor manufacturing supply chain for the latest insights, trends and innovations as the industry powers… Read More »SEMICON Japan + Advanced Packaging and Chiplet Summit
The First Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to… Read More »Chiplet Summit
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA,… Read More »CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform