New EDA Tools for 5G and AI Infrastructure Design We are ready to share the latest release of our electronic design automation (EDA) software suites. This update will help you design smarter with faster multidomain… Keysight EDA 2025 Launch event
The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC, GPU, mobile, and AI/ML. Multi-die design technology has been quickly evolving with early… Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
Position Your Company as a Leader in an Emerging Technology. Lay Claim to Your Share of a Projected $5.8 Billion Market (Omdia). Share Thoughts with Key Experts and Analysts. Show Movers and Shakers How Your… Chiplet Summit 2025
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include… Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include… Innovative Approach to SoC Power Optimization
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that… Exploring the Advancement of Chiplet Technology and the Ecosystem
The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power,… Chiplet Summit
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an open industry standard, to communicate… Why Chiplets with UCIe are the Next Big Thing
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express… UCIe-Based Chiplet Verification – from IP to SoC