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Mirabilis, October 15, 2024

ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted

There are so many options for Network-on-Chip: ARM-Corelink CMN700, Arteris FlexNoC, open-source NoC interconnect, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside… ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted

FMS 2024

Future of Memory and Storage – 2024

FMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest… Future of Memory and Storage – 2024

Siemens, February 21, 2024

Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity

Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1, 2.0 and 3.0, Siemens Avery CXL Verification IP. Compute Express Link (CXL) is an… Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity

Rambus, November 2, 2022

How CXL Technology will Revolutionize the Data Center

Data Centers face many challenges in an environment of exponentially rising data volume growth. With workload demands increasing rapidly, the need for more bandwidth and capacity continues to rise. Join us for a live webinar… How CXL Technology will Revolutionize the Data Center

Siemens EDA

Protocol and Memory Interface Verification in the Shrinking World of 3DIC

Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of… Protocol and Memory Interface Verification in the Shrinking World of 3DIC

Cadence CXL, January 27, 2002

Boost Your CXL Verification from IP to System Level

Register now for this CadenceTECHTALK, where we will walk you through CXL verification challenges from IP level to system level and demonstrate how these challenges can be significantly mitigated using the Cadence® Verification IP (VIP)… Boost Your CXL Verification from IP to System Level