Skip to content
Siemens EDA, June 8-9, 2022

Customers Discuss Their Real World Use of High-Level Synthesis

Summary The focus of this seminar is to have real-world customers present their successes using Catapult High-Level Synthesis (HLS) in markets such as Automotive, 5G/Communications, Video/Imaging, AI/ML, and MEMs Sensors. The companies who will be… Customers Discuss Their Real World Use of High-Level Synthesis

agnisys, april 28, 2022

Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™

Learn how to formally verify your design by automatically generating SystemVerilog Assertions (SVA) for your block-level register specifications, chip-level RTL, and RTL connectivity at the SoC level using ARV-Formal™.

Siemens EDA, April 12, 2022

Design Methodology for Building Power Efficient RTL

The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically… Design Methodology for Building Power Efficient RTL