ORConf 2024
Our 10th ORConf! The FOSSi Foundation is proud to announce the 10th installment of ORConf, a conference dedicated to free and open source silicon to… Read More »ORConf 2024
UVM
Efficient Way to UVM Constraint Randomization Debug
Become skilled at the art of UVM randomization debugging! Date: Wednesday, July 17, 2024 Time: 10:00am PDT | 1:00pm EDT This webinar equips you with effective strategies… Read More »Efficient Way to UVM Constraint Randomization Debug
Debugging Features of UVM
A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software, a verification environment written using… Read More »Debugging Features of UVM
Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and… Read More »Cracking the Power Code: Innovative Approach to SoC Power Optimization
Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and… Read More »Innovative Approach to SoC Power Optimization
Verification Futures Conference 2024 Austin
The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware… Read More »Verification Futures Conference 2024 Austin
Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious… Read More »Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
Verisium Debug for UVM Testbench
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar,… Read More »Verisium Debug for UVM Testbench
DVCon Japan 2023
The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification… Read More »DVCon Japan 2023
Verisium Debug for UPF Low Power Design
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In… Read More »Verisium Debug for UPF Low Power Design