Webinar
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2 events,
Improving Design Power and Performance with RTL Architect
Improving Design Power and Performance with RTL Architect
Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code. The first difficulty occurs during elaboration and synthesis. The RTL is converted to gates and the references to the source code are lost. The second difficulty is the gate-centric, implementation, PPA reports.… Read More »Improving Design Power and Performance with RTL Architect
A Faster Path to Analog IC Layout
A Faster Path to Analog IC Layout
Hey analog layout engineer! Start your journey in 2022 the right way, book a place in this webinar. In 'A faster path to analog layout' Mark Waller will show you how to shrink your design time by 60%. You are just one (free) click away: https://pulsic.link/WEBNRTwitter
1 event,
Accelerating Complex SoCs Prototyping with Protium X2
Accelerating Complex SoCs Prototyping with Protium X2
This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case study—RTL changes required for clocks management, memories, interfaces, multi-FPGA partitioning, and multi-user support. Join our CadenceTECHTALK to learn how the… Read More »Accelerating Complex SoCs Prototyping with Protium X2
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Increase your productivity with Continuous Integration flows
Increase your productivity with Continuous Integration flows
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to pinpoint which one introduced new bugs, and much time can… Read More »Increase your productivity with Continuous Integration flows
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Introduction to Questa Lint and CDC for Designers
Introduction to Questa Lint and CDC for Designers
Have you ever had RTL code that passes simulation but still fails due to things like unreachable code, out-of-range violations, or incorrect order of execution? Have you ever dealt with a multi-clock design that had glitch or reconvergence issues in silicon that took weeks to root cause? See how the correct verification tools can resolve… Read More »Introduction to Questa Lint and CDC for Designers
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3 events,
Boost Your CXL Verification from IP to System Level
Boost Your CXL Verification from IP to System Level
Register now for this CadenceTECHTALK, where we will walk you through CXL verification challenges from IP level to system level and demonstrate how these challenges can be significantly mitigated using the Cadence® Verification IP (VIP) solution for advanced verification methodologies. Specifically, this webinar will cover following topics: Growing market needs for CXL Verification challenges of… Read More »Boost Your CXL Verification from IP to System Level
Learn How to Perform Device Meshing with Silvaco’s Victory Mesh TCAD Solution
Learn How to Perform Device Meshing with Silvaco’s Victory Mesh TCAD Solution
ictory Mesh is Silvaco’s TCAD solution for device meshing and solid modeling. Victory Mesh creates suitable meshes from process structures for device simulation. For example, the results produced by process simulation software, such as Victory Process, are remeshed in Victory Mesh to produce input for device simulation software, such as Victory Device. Victory Mesh provides… Read More »Learn How to Perform Device Meshing with Silvaco’s Victory Mesh TCAD Solution
Future of Semiconductor Design: 2022 Predictions & Trends
Future of Semiconductor Design: 2022 Predictions & Trends
As the semiconductor industry continues to grow at an exponential rate, so has its challenges. We recently surveyed semiconductor design professionals on the biggest challenges, trends, and opportunities facing the industry today. Join Methodics experts, Simon Butler (General Manager) and Vishal Moondhra (Vice President Solutions) to review our findings and learn how you can thrive… Read More »Future of Semiconductor Design: 2022 Predictions & Trends
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Everything You Need to Know about SystemVerilog Arrays
Everything You Need to Know about SystemVerilog Arrays
This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array methods and practical examples. Topics: Review of Verilog array types SystemVerilog packed and unpacked arrays SystemVerilog dynamic arrays SystemVerilog queues SystemVerilog associate arrays Array manipulation methods. Coding examples are shown… Read More »Everything You Need to Know about SystemVerilog Arrays