Webinar
Calendar of Events
S Sun
M Mon
T Tue
W Wed
T Thu
F Fri
S Sat
0 events,
0 events,
0 events,
0 events,
0 events,
1 event,
Everything You Need to Know about SystemVerilog Arrays
Everything You Need to Know about SystemVerilog Arrays
This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array methods and practical examples. Topics: Review of Verilog array types SystemVerilog packed and unpacked arrays SystemVerilog dynamic arrays SystemVerilog queues SystemVerilog associate arrays Array manipulation methods. Coding examples are shown… Read More »Everything You Need to Know about SystemVerilog Arrays
0 events,
0 events,
0 events,
0 events,
1 event,
Exploring a Software First Approach to Avoid SoC Re-spins
Exploring a Software First Approach to Avoid SoC Re-spins
Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems. To conquer the verification challenge of complex SoCs, companies are shifting their development paradigm to a software first approach. By considering the target software up front, as a critical part of the SoC development process, designs… Read More »Exploring a Software First Approach to Avoid SoC Re-spins
4 events,
3DIC Design from Concept to Silicon
3DIC Design from Concept to Silicon
For some high-performance computing (HPC) designs, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges, such as reliable die-to-die connectivity, high bandwidth memory, integration, and 2.5D or 3D packaging options. This webinar will outline the different market trends for 3DIC… Read More »3DIC Design from Concept to Silicon
Managing the Complexity of FinFET Standard Cell Layout with Cello
Managing the Complexity of FinFET Standard Cell Layout with Cello
FinFET technologies have enabled designs with increased density and performance while reducing power, when compared to MOSFET. However, this comes at a cost of increased design complexity. Not only are some undesirable layout dependent effects more pronounced, but design rules have become much more complex. Many design rules violations can no longer be fixed within… Read More »Managing the Complexity of FinFET Standard Cell Layout with Cello
Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)
Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)
PCIe-based FPGA designs are becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with multiple high-speed serial interfaces such as PCIe produce non-deterministic results during physical tests. Simulation results are optimized because they are… Read More »Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)
0 events,
0 events,
0 events,
0 events,
1 event,
Optimized Chip Design with Main Processors and AI Accelerators
Optimized Chip Design with Main Processors and AI Accelerators
Presented by Paul Karazuba, VP of Marketing, Expedera & John Min, Director of Field Application Engineering, Andes Technology About this talk As AI capability is beginning large-scale deployment into edge devices, many wonder about the decision to use a specialized AI accelerator, rather than simply using the systems main processor. In this first of two… Read More »Optimized Chip Design with Main Processors and AI Accelerators
0 events,
4 events,
Balancing analog layout parasitics in MOSFET differential pairs
Balancing analog layout parasitics in MOSFET differential pairs
The MOSFET differential pair is a key part of many analog circuits e.g. opamps, comparators, LDOs, etc. A differential pair applies gain to the difference between two signals and has many advantages over single-ended amplifier circuits, e.g. noise reduction and suppression of common-mode signals and DC offset. However, these advantages rely upon precisely matched circuit… Read More »Balancing analog layout parasitics in MOSFET differential pairs
How to Improve Physical Verification Productivity with SmartDRC/LVS
How to Improve Physical Verification Productivity with SmartDRC/LVS
Physical Verification is the most critical stage of IC design. SmartDRC/LVS is a new physical verification tool for analog, digital and mixed-signal ICs including design rule checks (DRC), layout connectivity extraction and layout vs schematic (LVS) comparisons. Its unique multi-CPU architecture delivers high performance and capacity, accurate processing of complex shapes, and exceptional user productivity… Read More »How to Improve Physical Verification Productivity with SmartDRC/LVS
Open-Source FPGA: Towards Fully Automated FPGA Tapeout Flows
Open-Source FPGA: Towards Fully Automated FPGA Tapeout Flows
In this webinar, we will present the open-source FPGA tools which automate the tapeout flow for custom FPGA fabrics. We will cover the key steps involved in the process when using the tools, including netlist generation, design verification and performance prediction. We will also introduce the latest features in open-source FPGA and explain how they… Read More »Open-Source FPGA: Towards Fully Automated FPGA Tapeout Flows
0 events,
0 events,
0 events,
0 events,
1 event,
SemIsrael Tech Webinar
SemIsrael Tech Webinar
SemIsrael Expo is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design… Read More »SemIsrael Tech Webinar
3 events,
Connect Your System Architecture Design and Implementation
Connect Your System Architecture Design and Implementation
Join Cadence Training and Senior Application Engineer Dave Palumbo for this free technical Training Webinar. The disconnect between system architecture design and implementation makes creating a system that meets cost, performance, and form factor requirements challenging. Hardware designers need tools that help them engineer systems to meet the goals of their end products within the… Read More »Connect Your System Architecture Design and Implementation
The Role of PUFs in a Trusted Supply Chain
The Role of PUFs in a Trusted Supply Chain
Trusted supply chain provenance and traceability is becoming increasingly important for the quality, reliability, and security of electronic products. It can help reduce costs for tracking and fixing field issues, minimize liability risks and enable higher value in connected IoT applications. In addition, there are significant efficiencies and cost reductions that could be enabled in… Read More »The Role of PUFs in a Trusted Supply Chain
CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during planning and implementation. The new Cadence® Integrity™ 3D-IC platform provides innovative technology that proactively looks ahead through integrated planning, implementation,… Read More »CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
4 events,
How to Use Device Simulation as a Tool for Understanding GaN HEMTS
How to Use Device Simulation as a Tool for Understanding GaN HEMTS
Gallium Nitride based devices are highly attractive for both RF and power switching applications due to a combination of outstanding materials properties. However, although the basic principles are well understood and can now be accurately reproduced in device simulators, there are many important aspects that are still poorly understood and the subject of continuing active… Read More »How to Use Device Simulation as a Tool for Understanding GaN HEMTS
Automating UVM flow using Riviera-PRO’s UVM Generator
Automating UVM flow using Riviera-PRO’s UVM Generator
UVM is a versatile verification methodology that enables users to run advanced verification flows for large scale FPGAs and SoC FPGAs. However, because of its advanced nature, writing UVM from scratch can be a complex and tedious task. Riviera-PRO’s new UVM Generator feature alleviates some of the complexity by automatically creating the UVM testbench for… Read More »Automating UVM flow using Riviera-PRO’s UVM Generator
How to use MaxPlace to improve Timing and Congestion of Display Driver IC
How to use MaxPlace to improve Timing and Congestion of Display Driver IC
Agenda: •Maxeda Highlight •Product Overview •Display Driver IC Challenges for Congestion/Timing •MaxPlace Solutions for Display Driver IC •Our next step - ML •Q&A
0 events,
0 events,
0 events,
0 events,
1 event,
PCB fab & assembly quote demonstration
PCB fab & assembly quote demonstration
Sierra Circuits created a plugin for the popular KiCad EDA tool used by PCB designers, and it provides you a quick quote on your project. How does this benefit you? Well, our plugin saves you time since you no longer need to output your data to send it to the PCB house. This also spares… Read More »PCB fab & assembly quote demonstration
1 event,
Python in Verification, Online Meetup
Python in Verification, Online Meetup
At Veriest, we believe in knowledge sharing. In our recent meetup events, hundreds of professionals from 20+ different countries gathered to listen to different industry experts from companies such as Intel, ST Microelectronics, arm, Texas Instruments, Nvidia and more. This time, we'll focus on the polemic topic of using Python in Verification. We'll have two presentations, both… Read More »Python in Verification, Online Meetup
1 event,
Semiconductor Device Improvement Using Atomera MST Technologies and MSTcad Toolset.
Semiconductor Device Improvement Using Atomera MST Technologies and MSTcad Toolset.
Join our webinar to learn about how Atomera’s MSTcad™ toolset can be used to model and optimize transistor performance when integrating Atomera’s Mears Silicon Technology™ (MST) into a semiconductor process. Topics covered include how MST® enhances most transistor characteristics, and how the MSTcad toolset provides sophisticated modeling capabilities for analyzing MST’s dopant blocking capabilities, how users… Read More »Semiconductor Device Improvement Using Atomera MST Technologies and MSTcad Toolset.